Patent US3723976A successfully refreshed from Google Patents.
US3723976A
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Memory system with logical and real addressing
Assignee: International Business Machines Corp
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Filing: 1972-01-20
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Granted: 1973-03-27
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Expires: 1992-01-20
Abstract
Abstract A memory system is disclosed for use in a multiprocessing environment where each processor has associated with it a buffer memory and means are provided for one buffer to retain a modified copy of data. The contents of the buffer memory may be accessed by either real or logical addresses. Address translation means are provided to translate logical addresses. A fetch directory is provided to keep track of the data in cache. The fetch directory entries are accessed by both logical and real portions of the desired data address. Means are provided to insure that only one copy of data is maintained in the buffer although it may be entered at several cache locations dependent upon the logical address which last fetched the data.
Inventors
- 👤 J Alvarez
- 👤 R Barner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:29
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0864; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1063
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
177 words
A memory system in a data processor, said data processor containing a main memory and a processing unit, comprising: storage means associated with said processing unit and said main memory for storing selective portions of data from said main memory, register means for receiving from said processing unit an address of desired data in both logical and real form, directory means connected to said storage means and said register means for retaining in both logical and real form a portion of the data address of the data resident in the corresponding portion of said storage means, accessing means connected to said register means and said directory means for accessing said retained portion of data address resident in said directory means and means for determining if said desired data is resident in said storage means irrespective of the address used to store the desired data, whereby the memory system insures that data stored in the storage means may be located irrespective of whether the logical or real address was used to store the data into the storage means.
Claim 2
Dependent Claim
177 words
A memory system in a data processor, said data processor containing a main memory and a processing unit, comprising: storage means associated with said processing unit and said main memory for storing selective portions of data from said main memory, register means for receiving from said processing unit an address of desired data in both logical and real form, directory means connected to said storage means and said register means for retaining in both logical and real form a portion of the data address of the data resident in the corresponding portion of said storage means, accessing means connected to said register means and said directory means for accessing said retained portion of data address resident in said directory means and means for determining if said desired data is resident in said storage means irrespective of the address used to store the desired data, whereby the memory system insures that data stored in the storage means may be located irrespective of whether the logical or real address was used to store the data into the storage means.
Claim 3
Dependent Claim
58 words
The apparatus of claim 1 wherein said directory means comprises: a fetch directory that contains a portion of the real data address that fetched each corresponding piece of data into said storage means, and a broadcast store directory that contains a portion of the logical and real data address for each piece of data into said storage means.
Claim 4
Dependent Claim
60 words
The apparatus of claim 2 wherein said determining means comprise: translation means connected to said register means to translate a logical address to a real address, broadcast means connected to said translation means to transmit said translated real address, and real address register means connected to said broadcast means and said broadcast store directory for receiving said transmitted real addresses.
Claim 5
Dependent Claim
53 words
The apparatus of claim 3 further comprising replacement means to determine the status of data presently stored in the desired data address location, storing the presently stored data into said main memory if it is found to be in a valid modified state and storing new data in the just vacated addressed location.
Claim 6
Dependent Claim
36 words
The apparatus of claim 4 wherein said replacement means further updates said directory means entries to reflect the location of data in accordance with the logical address which last fetched said data into said storage means.
Claim 7
Dependent Claim
170 words
A memory system in a multiprocessor, said multiprocessor containing a main memory and a plurality of processing units, comprising: a plurality of storage means, one of said storage means associated with each of said plurality of processing units, for storing selective portions of data from said main memory, register means associated with each of said storage means for receiving from said associated processing unit an address of desired data in both logical and real form, directory means associated with each of said storage means connected to said storage means and said register means for retaining in both logical and real form a portion of the data address of the data resident in the corresponding portion of said storage means, accessing means connected to each of register means and each of said directory means for accessing said retained portion of data address resident in said directorY means and means for determining if said desired data is resident in said storage means irrespective of the address used to store the desired data.
Claim 8
Dependent Claim
170 words
A memory system in a multiprocessor, said multiprocessor containing a main memory and a plurality of processing units, comprising: a plurality of storage means, one of said storage means associated with each of said plurality of processing units, for storing selective portions of data from said main memory, register means associated with each of said storage means for receiving from said associated processing unit an address of desired data in both logical and real form, directory means associated with each of said storage means connected to said storage means and said register means for retaining in both logical and real form a portion of the data address of the data resident in the corresponding portion of said storage means, accessing means connected to each of register means and each of said directory means for accessing said retained portion of data address resident in said directorY means and means for determining if said desired data is resident in said storage means irrespective of the address used to store the desired data.
Claim 9
Dependent Claim
60 words
The apparatus of claim 6 wherein each of said directory means comprises: a fetch directory that contains a portion of the real data address that fetched each corresponding piece of data into said storage means, and a broadcast store directory that contains a portion of the logical and real data address for each piece of data into said storage means.
Claim 10
Dependent Claim
70 words
The apparatus of claim 7 wherein said determining means comprise: a plurality of translation means connected to each of said register means to translate a logical address to a real address, broadcast means connected to each of said translation means to transmit said translated real address, and a plurality of real address register means connected to said broadcast means and said broadcast store directory for receiving said transmitted real addresses.
Claim 11
Dependent Claim
62 words
The apparatus of claim 8 further comprising a plurality of replacement means one associated with each storage means to determine the status of data presently stored in the desired data address location, storing the presently stored data into said main memory if it is found to be in a valid modified state and storing new data in the just vacated addressed location.
Claim 12
Dependent Claim
38 words
The apparatus of claim 9 wherein each of said replacement means further updates said directory means entries to reflect the location of data in accordance with the logical address which last fetched said data into said storage means.
Claim 13
Dependent Claim
39 words
The apparatus of claim 10 wherein said broadcasting means is connected to each of said real address register means in all memory systems and transmits said translated real address to the real address register means in all memory systems.
References Cited (Backward Citations)
US26429A
Cited
US3388381A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-03-26 | 1976-09-25 | 1977-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-03-26 | 1980-09-25 | 1981-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-03-26 | 1984-09-25 | 1985-03-27 | $7700.00 | Window Closed / Lapsed |