Patent US3717850A successfully refreshed from Google Patents.
US3717850A
Expired / Lapsed
US
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Programmed data processing with facilitated transfers
Assignee: AT&T Inc
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Filing: 1972-03-17
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Granted: 1973-02-20
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Expires: 1992-03-17
Abstract
Abstract An overlap mode computer is disclosed in which delays in making transfers are minimized by placing the transfer instruction in a position in the subset of instructions prior to the last position. The position of the transfer instruction is selected such that its execution in the overlapped sequence of executions is completed immediately after the accessing of the last instruction of the subset transferred from.
Inventors
- 👤 H Ghiron
- 👤 W Ulrich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:48
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3842
Claims Analysis
Total Claims: 80
Claim 1
Independent Claim
21 words
initiating the execution of some, but not all, of the instructions of a first suBset of instructions during successive machine cycles,
Claim 2
Dependent Claim
21 words
initiating the execution of some, but not all, of the instructions of a first suBset of instructions during successive machine cycles,
Claim 3
Dependent Claim
177 words
Cyclically operating data processing apparatus comprising means for storing first and second subsets of instruction signals, the members of the first subset including transfer instruction signals, means for initiating, at substantially the beginning of each data processing cycle, the extraction of instruction signals from the storing means, a first register and a second register, first means for gating instruction signals, extracted from said storing means, to the first of the registers at substantially the beginning of each data processing cycle, second means for gating transfer instruction signals, extracted from said storing means, from said first register to said second register after the operation of the first-mentioned gating means, and third means for gating said transfer instruction signals from said second register to the initiating means at the time the last member of said first subset is being extracted from said storing means, whereby a transfer instruction preceding the last instruction of said first subset initiates the extraction of instruction signals of said second subset immediately following the extraction of the last instruction signals of said first subset.
Claim 4
Dependent Claim
177 words
Cyclically operating data processing apparatus comprising means for storing first and second subsets of instruction signals, the members of the first subset including transfer instruction signals, means for initiating, at substantially the beginning of each data processing cycle, the extraction of instruction signals from the storing means, a first register and a second register, first means for gating instruction signals, extracted from said storing means, to the first of the registers at substantially the beginning of each data processing cycle, second means for gating transfer instruction signals, extracted from said storing means, from said first register to said second register after the operation of the first-mentioned gating means, and third means for gating said transfer instruction signals from said second register to the initiating means at the time the last member of said first subset is being extracted from said storing means, whereby a transfer instruction preceding the last instruction of said first subset initiates the extraction of instruction signals of said second subset immediately following the extraction of the last instruction signals of said first subset.
Claim 5
Dependent Claim
21 words
sequentially processing the instructions of a sequence of instructions, including an instruction for transferring to a nonsequential instruction of said machine,
Claim 6
Dependent Claim
21 words
sequentially processing the instructions of a sequence of instructions, including an instruction for transferring to a nonsequential instruction of said machine,
Claim 7
Dependent Claim
177 words
Cyclically operating data processing apparatus comprising means for storing first and second subsets of instruction signals, the members of the first subset including transfer instruction signals, means for initiating, at substantially the beginning of each data processing cycle, the extraction of instruction signals from the storing means, a first register and a second register, first means for gating instruction signals, extracted from said storing means, to the first of the registers at substantially the beginning of each data processing cycle, second means for gating transfer instruction signals, extracted from said storing means, from said first register to said second register after the operation of the first-mentioned gating means, and third means for gating said transfer instruction signals from said second register to the initiating means at the time the last member of said first subset is being extracted from said storing means, whereby a transfer instruction preceding the last instruction of said first subset initiates the extraction of instruction signals of said second subset immediately following the extraction of the last instruction signals of said first subset.
Claim 8
Dependent Claim
177 words
Cyclically operating data processing apparatus comprising means for storing first and second subsets of instruction signals, the members of the first subset including transfer instruction signals, means for initiating, at substantially the beginning of each data processing cycle, the extraction of instruction signals from the storing means, a first register and a second register, first means for gating instruction signals, extracted from said storing means, to the first of the registers at substantially the beginning of each data processing cycle, second means for gating transfer instruction signals, extracted from said storing means, from said first register to said second register after the operation of the first-mentioned gating means, and third means for gating said transfer instruction signals from said second register to the initiating means at the time the last member of said first subset is being extracted from said storing means, whereby a transfer instruction preceding the last instruction of said first subset initiates the extraction of instruction signals of said second subset immediately following the extraction of the last instruction signals of said first subset.
Claim 9
Dependent Claim
8 words
storing signals representing the instructions of the subsets,
Claim 10
Dependent Claim
8 words
storing signals representing the instructions of the subsets,
Claim 11
Dependent Claim
11 words
entering an instruction of a first subset into a first register,
Claim 12
Dependent Claim
11 words
entering an instruction of a first subset into a first register,
Claim 13
Dependent Claim
35 words
storing the instructions of the one set in sequential locations of a store, and including an instruction for transferring from said one set to the other set at an intermediate location of said sequential locations,
Claim 14
Dependent Claim
35 words
storing the instructions of the one set in sequential locations of a store, and including an instruction for transferring from said one set to the other set at an intermediate location of said sequential locations,
Claim 15
Dependent Claim
33 words
addressing a transfer instruction, for transferring from a first set of instructions to a second set of instructions, and decoding an instruction of said first subset of instructions during a first machine cycle,
Claim 16
Dependent Claim
33 words
addressing a transfer instruction, for transferring from a first set of instructions to a second set of instructions, and decoding an instruction of said first subset of instructions during a first machine cycle,
Claim 17
Dependent Claim
34 words
storing the instructions of the one set in sequential locations of a store and including an instruction for transferring from said one set to the other set at an intermediate location of said sequence,
Claim 18
Dependent Claim
34 words
storing the instructions of the one set in sequential locations of a store and including an instruction for transferring from said one set to the other set at an intermediate location of said sequence,
Claim 19
Dependent Claim
17 words
storing the instructions of said other set in sequential locations, different from the first, of said store,
Claim 20
Dependent Claim
17 words
storing the instructions of said other set in sequential locations, different from the first, of said store,
Claim 21
Dependent Claim
17 words
storing the instructions of said other set in sequential locations, different from the first, of said store,
Claim 22
Dependent Claim
17 words
storing the instructions of said other set in sequential locations, different from the first, of said store,
Claim 23
Dependent Claim
20 words
addressing a succeeding instruction of said first subset of instructions and decoding said transfer instruction during a second machine cycle,
Claim 24
Dependent Claim
20 words
addressing a succeeding instruction of said first subset of instructions and decoding said transfer instruction during a second machine cycle,
Claim 25
Dependent Claim
27 words
entering said instruction into a second register during the same machine cycle that an instruction to transfer to a second subset is entered into said first register,
Claim 26
Dependent Claim
27 words
entering said instruction into a second register during the same machine cycle that an instruction to transfer to a second subset is entered into said first register,
Claim 27
Dependent Claim
13 words
storing signals, representing an instruction dictating a transfer from one subset to another,
Claim 28
Dependent Claim
13 words
storing signals, representing an instruction dictating a transfer from one subset to another,
Claim 29
Dependent Claim
64 words
Apparatus for cyclically operating on an overlap basis comprising storage means, means for addressing said storage means sequentially during a current machine cycle to extract signals therefrom during the next cycle, means for decoding during said current cycle, signals extracted during the previous cycle, and means responsive to the decoding means for establishing a nonsequential address in the addressing means during said next cycle.
Claim 30
Dependent Claim
64 words
Apparatus for cyclically operating on an overlap basis comprising storage means, means for addressing said storage means sequentially during a current machine cycle to extract signals therefrom during the next cycle, means for decoding during said current cycle, signals extracted during the previous cycle, and means responsive to the decoding means for establishing a nonsequential address in the addressing means during said next cycle.
Claim 31
Dependent Claim
8 words
executing a further instruction of said sequence, and
Claim 32
Dependent Claim
8 words
executing a further instruction of said sequence, and
Claim 33
Dependent Claim
29 words
initiating, but not completing, a transfer to the first instruction of a second subset during the same machine cycle that an instruction of said first subset is being executed,
Claim 34
Dependent Claim
29 words
initiating, but not completing, a transfer to the first instruction of a second subset during the same machine cycle that an instruction of said first subset is being executed,
Claim 35
Dependent Claim
13 words
executing the remaining instructions of said first subset during successive machine cycles, and
Claim 36
Dependent Claim
13 words
executing the remaining instructions of said first subset during successive machine cycles, and
Claim 37
Dependent Claim
8 words
completing said transfer and executing said nonsequential instruction.
Claim 38
Dependent Claim
8 words
completing said transfer and executing said nonsequential instruction.
Claim 39
Dependent Claim
90 words
In an overlap data processing apparatus for which a memory is being addressed for a first instruction at the same time a second instruction is being extracted therefrom and a third instruction is Being executed, apparatus for facilitating a transfer from one subset of instructions to another which comprises means for executing all of the instructions of a first subset on an overlap basis, and means for initiating a transfer to a second subset of instructions during the extraction of at least one of the instructions of said first subset.
Claim 40
Dependent Claim
90 words
In an overlap data processing apparatus for which a memory is being addressed for a first instruction at the same time a second instruction is being extracted therefrom and a third instruction is Being executed, apparatus for facilitating a transfer from one subset of instructions to another which comprises means for executing all of the instructions of a first subset on an overlap basis, and means for initiating a transfer to a second subset of instructions during the extraction of at least one of the instructions of said first subset.
Claim 41
Dependent Claim
18 words
commencing to extract from storage, and commencing to execute, said signals representing the instructions of the one subset,
Claim 42
Dependent Claim
18 words
commencing to extract from storage, and commencing to execute, said signals representing the instructions of the one subset,
Claim 43
Dependent Claim
30 words
entering said transfer instructions into said second register from said first register during the same machine cycle that another instruction of said first subset is entered into said first register,
Claim 44
Dependent Claim
30 words
entering said transfer instructions into said second register from said first register during the same machine cycle that another instruction of said first subset is entered into said first register,
Claim 45
Dependent Claim
31 words
addressing the first instruction of said second subset of instructions, as dictated by said transfer instructions, and decoding said succeeding instruction of said first subset during a third machine cycle, and
Claim 46
Dependent Claim
31 words
addressing the first instruction of said second subset of instructions, as dictated by said transfer instructions, and decoding said succeeding instruction of said first subset during a third machine cycle, and
Claim 47
Dependent Claim
13 words
initiating the extraction of the instructions of said one set in sequence, and
Claim 48
Dependent Claim
13 words
initiating the extraction of the instructions of said one set in sequence, and
Claim 49
Dependent Claim
12 words
initiating the extraction of the instructions of said one set in sequence,
Claim 50
Dependent Claim
12 words
initiating the extraction of the instructions of said one set in sequence,
Claim 51
Dependent Claim
64 words
processing the instructions thus extracted on an overlap basis in which one instruction is at least partially extracted during the same machine cycle that the succeeding instruction is being extracted from said store, whereby the intermediate position of the transfer instruction permits the first instruction of said other set to be executed immediately following the execution of the last instruction of said one set.
Claim 52
Dependent Claim
64 words
processing the instructions thus extracted on an overlap basis in which one instruction is at least partially extracted during the same machine cycle that the succeeding instruction is being extracted from said store, whereby the intermediate position of the transfer instruction permits the first instruction of said other set to be executed immediately following the execution of the last instruction of said one set.
Claim 53
Dependent Claim
70 words
processing the instructions thus extracted on an overlap basis for which one instruction is being at least partially executed at the same time the succeeding instruction is being extracted from said store, whereby an instruction of the one subset, to which a transfer is made in accordance with the transfer instruction, is extracted from said store at the same time the last instruction of the other subset is being executed.
Claim 54
Dependent Claim
70 words
processing the instructions thus extracted on an overlap basis for which one instruction is being at least partially executed at the same time the succeeding instruction is being extracted from said store, whereby an instruction of the one subset, to which a transfer is made in accordance with the transfer instruction, is extracted from said store at the same time the last instruction of the other subset is being executed.
Claim 55
Dependent Claim
24 words
addressing the second instruction of said second subset of instructions and decoding the first instruction of said second subset during a fourth machine cycle.
Claim 56
Dependent Claim
24 words
addressing the second instruction of said second subset of instructions and decoding the first instruction of said second subset during a fourth machine cycle.
Claim 57
Dependent Claim
28 words
executing the first instruction of said second subset, prescribed by said transfer, during the machine cycle immediately following the execution of the last instruction of said first subset.
Claim 58
Dependent Claim
28 words
executing the first instruction of said second subset, prescribed by said transfer, during the machine cycle immediately following the execution of the last instruction of said first subset.
Claim 59
Dependent Claim
24 words
extracting from storage, and executing, said signals representing the transfer instruction before executing the signals representing the last instruction of said one subset, and
Claim 60
Dependent Claim
24 words
extracting from storage, and executing, said signals representing the transfer instruction before executing the signals representing the last instruction of said one subset, and
Claim 61
Dependent Claim
89 words
Program data processing apparatus for facilitating a transfer from one subset of instructions to another which comprises means for storing signals representing (1) the instructions of the subsets and (2) an instruction directing a transfer from one subset to another, means for extracting said signals from storage, and means extracting the transfer signals from storage before all the signals of said one subset are extracted and means producing a transfer to the signals of the other subset immediately following the execution of the last signals of said one subset.
Claim 62
Dependent Claim
89 words
Program data processing apparatus for facilitating a transfer from one subset of instructions to another which comprises means for storing signals representing (1) the instructions of the subsets and (2) an instruction directing a transfer from one subset to another, means for extracting said signals from storage, and means extracting the transfer signals from storage before all the signals of said one subset are extracted and means producing a transfer to the signals of the other subset immediately following the execution of the last signals of said one subset.
Claim 63
Dependent Claim
50 words
entering said other instruction into said second register from said first register during the same machine cycle that the first instruction dictated by a said transfer instruction is entered into said first register, thereby to facilitate the execution of an instruction for transferring from one subset of instructions to another.
Claim 64
Dependent Claim
50 words
entering said other instruction into said second register from said first register during the same machine cycle that the first instruction dictated by a said transfer instruction is entered into said first register, thereby to facilitate the execution of an instruction for transferring from one subset of instructions to another.
Claim 65
Dependent Claim
66 words
Apparatus comprising storage means having a plurality of storage locations, means or extracting signals from a first set of sequential locations of said storage means, and means, responsive to an intermediate one of the extracted signals, for initiating a transfer before the last instruction of the first sequence is executed and completing said transfer immediately following the execution of said last instruction of the first sequence.
Claim 66
Dependent Claim
66 words
Apparatus comprising storage means having a plurality of storage locations, means or extracting signals from a first set of sequential locations of said storage means, and means, responsive to an intermediate one of the extracted signals, for initiating a transfer before the last instruction of the first sequence is executed and completing said transfer immediately following the execution of said last instruction of the first sequence.
Claim 67
Dependent Claim
33 words
executing the signals representing the last instruction of said one subset immediately followed by executing the signals of said other subset to which a transfer is made in accordance with said transfer instruction.
Claim 68
Dependent Claim
33 words
executing the signals representing the last instruction of said one subset immediately followed by executing the signals of said other subset to which a transfer is made in accordance with said transfer instruction.
Claim 69
Dependent Claim
23 words
In programmed data processing, the method of facilitating a transfer from one subset of program instructions to another, which comprises the steps of
Claim 70
Dependent Claim
23 words
In programmed data processing, the method of facilitating a transfer from one subset of program instructions to another, which comprises the steps of
Claim 71
Independent Claim
22 words
The method of processing data during synchronous machine cycles under the control of two subsets of instructions, which comprises the steps of
Claim 72
Independent Claim
22 words
The method of processing data during synchronous machine cycles under the control of two subsets of instructions, which comprises the steps of
Claim 73
Independent Claim
20 words
The method of processing data under the control of instructions in a data processing system, which comprises the steps of
Claim 74
Independent Claim
20 words
The method of processing data under the control of instructions in a data processing system, which comprises the steps of
Claim 75
Dependent Claim
38 words
In a data processing system operating under the control of sequential instructions on an overlap basis during synchronous machine cycles, the method of facilitating a transfer from one subset of instructions to another, which comprises the steps of
Claim 76
Dependent Claim
38 words
In a data processing system operating under the control of sequential instructions on an overlap basis during synchronous machine cycles, the method of facilitating a transfer from one subset of instructions to another, which comprises the steps of
Claim 77
Dependent Claim
55 words
In a data processing system operating cyclically under the control of instructions on an overlap basis for which one instruction is being addressed during the same machine cycle that another instruction is being decoded, the method of facilitating a transfer of system operation from one subset of instructions to another, which comprises the steps of
Claim 78
Dependent Claim
55 words
In a data processing system operating cyclically under the control of instructions on an overlap basis for which one instruction is being addressed during the same machine cycle that another instruction is being decoded, the method of facilitating a transfer of system operation from one subset of instructions to another, which comprises the steps of
Claim 79
Dependent Claim
23 words
In programmed data processing, the method of facilitating a transfer from one set of program instructions to another, which comprises the steps of
Claim 80
Dependent Claim
23 words
In programmed data processing, the method of facilitating a transfer from one set of program instructions to another, which comprises the steps of
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-20 | 1976-08-21 | 1977-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-20 | 1980-08-21 | 1981-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-20 | 1984-08-21 | 1985-02-20 | $7700.00 | Window Closed / Lapsed |