US3716849A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrating measurements with noise reduction
Assignee: SOLARTON ELECTRONIC
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Filing: 1970-06-08
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Granted: 1973-02-13
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Expires: 1990-06-08
Abstract
Abstract Noise rejection in an integrating type of analogue to digital converter is improved by effecting the integration in accordance with a variable weighting function, preferably a step function. Functions are described which flatten the response versus frequency curve in the neighborhood of the zeroes and introduce more zeroes into this curve. The weighting may be introduced by scaling either on the analogue side or the digital side of the instrument.
Inventors
- 👤 E Metcalf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:31
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/52
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
111 words
In an analog to digital conversion circuit for converting an analog signal which can include undesirable alternating noise signal components to a digital representation thereof the combination of timing means for defining a measurement period whose duration is an integral multiple of the period of at least one of said noise signal components; integrating means for integrating the analog signal over said measurement period; and control means responsive to said timing means for varying the weight with which the analog signal is integrated during said measurement period in accordance with a predetermined weighting function, which function is selected to enhance rejection of said at least one of said noise signal components.
Claim 2
Dependent Claim
111 words
In an analog to digital conversion circuit for converting an analog signal which can include undesirable alternating noise signal components to a digital representation thereof the combination of timing means for defining a measurement period whose duration is an integral multiple of the period of at least one of said noise signal components; integrating means for integrating the analog signal over said measurement period; and control means responsive to said timing means for varying the weight with which the analog signal is integrated during said measurement period in accordance with a predetermined weighting function, which function is selected to enhance rejection of said at least one of said noise signal components.
Claim 3
Dependent Claim
111 words
In an analog to digital conversion circuit for converting an analog signal which can include undesirable alternating noise signal components to a digital representation thereof the combination of timing means for defining a measurement period whose duration is an integral multiple of the period of at least one of said noise signal components; integrating means for integrating the analog signal over said measurement period; and control means responsive to said timing means for varying the weight with which the analog signal is integrated during said measurement period in accordance with a predetermined weighting function, which function is selected to enhance rejection of said at least one of said noise signal components.
Claim 4
Dependent Claim
111 words
In an analog to digital conversion circuit for converting an analog signal which can include undesirable alternating noise signal components to a digital representation thereof the combination of timing means for defining a measurement period whose duration is an integral multiple of the period of at least one of said noise signal components; integrating means for integrating the analog signal over said measurement period; and control means responsive to said timing means for varying the weight with which the analog signal is integrated during said measurement period in accordance with a predetermined weighting function, which function is selected to enhance rejection of said at least one of said noise signal components.
Claim 5
Dependent Claim
19 words
A circuit according to claim 1, wherein the weighting function first increases and then decreases during the measurement period.
Claim 6
Dependent Claim
16 words
A circuit according to claim 2, wherein the weighting function increases and then decreases substantially continuously.
Claim 7
Dependent Claim
19 words
A circuit according to claim 1, wherein the weighting function is symmetrical about the middle of the measurement period.
Claim 8
Dependent Claim
14 words
A circuit according to claim 1, wherein the weighting function is a step function.
Claim 9
Dependent Claim
27 words
A circuit according to claim 5, wherein the weighting function first increases stepwise by at least one step and then decreases stepwise by at least one step.
Claim 10
Dependent Claim
45 words
A circuit according to claim 6, wherein the weighting function has an initial non-zero value, increases to three times this value one quarter of the way through the measurement period and decreases to the initial value three quarters of the way through the measurement period.
Claim 11
Dependent Claim
22 words
A circuit according to claim 5, wherein the weighting function alternates between two values a plurality of times during the measurement period.
Claim 12
Dependent Claim
29 words
A circuit according to claim 1, wherein the control means scales the analog signal applied to the integrating means in accordance with the weighting function during the measurement period.
Claim 13
Dependent Claim
50 words
A circuit according to claim 9, wherein said control means comprises a source of clock pulses, a counter for counting pulses from said clock to determine the measurement period and a switched attenuator preceding the integrating means for scaling the analogue signal, the switched attenuator being controlled by the counter.
Claim 14
Dependent Claim
39 words
A circuit according to claim 10, wherein the attenuation provided by the attenuator decreases in the first half of the measurement period by small steps, one per clock pulse, and thereafter increases by small steps, one per clock pulse.
Claim 15
Dependent Claim
43 words
A circuit according to claim 10, comprising a decoder for decoding a plurality of states of the counter corresponding to predetermined points within the measurement period, the switched attenuator being controlled by the decoder to vary the attenuation stepwise at the said points.
Claim 16
Dependent Claim
17 words
A circuit according to claim 12, wherein the attenuation alternates between two values at the said points.
Claim 17
Dependent Claim
61 words
A circuit according to claim 1, wherein the circuit further comprises a voltage to frequency converter responsive to the analogue signal and a counter for counting pulses from the voltage to frequency converter during the measurement period to form a digital count constituting the integral of the analogue signal, the control means scaling the pulses digitally as counted by the counter.
Claim 18
Dependent Claim
38 words
A circuit according to claim 14, wherein the control means comprise at least one pulse divider preceding the counter and switching means for switching this divider in and out of circuit at predetermined points within the measurement period.
Claim 19
Dependent Claim
51 words
A circuit according to claim 15, wherein the control means comprise a source of clock pulses, a furtheR counter for counting these pulses to determine the measurement period, and a decoder for decoding a plurality of states of the counter corresponding to the said points and for controlling the switching means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-13 | 1976-08-14 | 1977-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-13 | 1980-08-14 | 1981-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-13 | 1984-08-14 | 1985-02-13 | $7700.00 | Window Closed / Lapsed |