Patent US3705388A successfully refreshed from Google Patents.
US3705388A
Expired / Lapsed
US
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Memory control system which enables access requests during block transfer
Assignee: National Institute of Advanced Industrial Science and Technology
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Filing: 1970-08-06
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Granted: 1972-12-05
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Expires: 1990-08-06
Abstract
Abstract A buffer memory control system for a buffer memory having a shorter access time and a smaller number of memory locations than a main memory. If the requested information is not present in the buffer memory, the block including the requested information is transferred from the main memory to the buffer memory. When a read or write request for the information of another block which is different from the said block is made during the transfer of the latter block, the transfer of the block is interrupted temporarily to immediately effect the reading from or writing in the another block of the buffer memory, after the completion of which the transfer of the block is resumed if the requested information of the another block is present in the buffer memory.
Inventors
- 👤 Tetsunori Nishimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:38
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F12/0859; G06F13/00; G06F13/14; G06F13/16; G06F13/18
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
93 words
A method of controlling a buffer memory when a read or write request is made to said buffer memory during the transfer of a block of information from a main memory to said buffer memory for information of another block which is different from said block under transfer and when the requested information is present in said buffer memory, comprising the steps of temporarily interrupting said transfer to perform the read or write operation from or in said buffer memory, and resuming said transfer after the completion of said read or write operation.
Claim 2
Independent Claim
93 words
A method of controlling a buffer memory when a read or write request is made to said buffer memory during the transfer of a block of information from a main memory to said buffer memory for information of another block which is different from said block under transfer and when the requested information is present in said buffer memory, comprising the steps of temporarily interrupting said transfer to perform the read or write operation from or in said buffer memory, and resuming said transfer after the completion of said read or write operation.
Claim 3
Dependent Claim
140 words
In an information processing system comprising a main memory, and a buffer memory having a shorter access time and a smaller number of memory locations than said memory: a buffer memory control system comprising a first register for storing the addresses of a sector and a block containing information being under transfer from said main memory to said buffer memory, a second register for indicating the presence or absence of information in said first register, a circuit for comparing the address of the sector and block requested during said transfer and said address of said sector and block under transfer, a counter which is interrupted when said addresses do not coincide with each other in said comparing circuit, and means for generating a temporary interruption signal to be supplied to said main memory synchronously with the interruption of said counter.
Claim 4
Dependent Claim
140 words
In an information processing system comprising a main memory, and a buffer memory having a shorter access time and a smaller number of memory locations than said memory: a buffer memory control system comprising a first register for storing the addresses of a sector and a block containing information being under transfer from said main memory to said buffer memory, a second register for indicating the presence or absence of information in said first register, a circuit for comparing the address of the sector and block requested during said transfer and said address of said sector and block under transfer, a counter which is interrupted when said addresses do not coincide with each other in said comparing circuit, and means for generating a temporary interruption signal to be supplied to said main memory synchronously with the interruption of said counter.
Claim 5
Dependent Claim
188 words
In an information processing system comprising a main memory, and a buffer memory having a shorter access time and a smaller number of memory locations than said main memory: a buffer memory control system comprising a register in which an address for reading or writing information is set, means for indicating whether or not the information of the address set in said register is present in said buffer memory, means for transferring a block including the information for which read-out is requested from said main memory to said buffer memory when said information is not present in said buffer memory, means for holding the address of the sector and block of the information transferred by said transfer means, means for comparing said address set in said register and said address held by said holding means during said block transfer by said transferring means, and means for interrupting said block transfer upon the provision of an incoincidence signal by said comparing means, for processing said request by the presence in said buffer memory of the information of said address set in said register, and for resuming said block transfer.
Claim 6
Dependent Claim
188 words
In an information processing system comprising a main memory, and a buffer memory having a shorter access time and a smaller number of memory locations than said main memory: a buffer memory control system comprising a register in which an address for reading or writing information is set, means for indicating whether or not the information of the address set in said register is present in said buffer memory, means for transferring a block including the information for which read-out is requested from said main memory to said buffer memory when said information is not present in said buffer memory, means for holding the address of the sector and block of the information transferred by said transfer means, means for comparing said address set in said register and said address held by said holding means during said block transfer by said transferring means, and means for interrupting said block transfer upon the provision of an incoincidence signal by said comparing means, for processing said request by the presence in said buffer memory of the information of said address set in said register, and for resuming said block transfer.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-12-05 | 1976-06-05 | 1976-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-12-05 | 1980-06-05 | 1980-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-12-05 | 1984-06-05 | 1984-12-05 | $7700.00 | Window Closed / Lapsed |