Digital processor

Claim 2

A digital processor comprising read-only memory means for providing a serial sequence of instruction signals in a serial-by-bit manner to a memory buss; a plurality of storage registers each of which can assume a condition manifesting the storage thereby of at least one character of information, each of said registers being capable of being selected to provide a stored signal indicative of a stored character of information in a serial-by-bit manner to at least one of either a destination buss or an origin buss, each of said registers further being capable of being selected to respond to a signal appearing on an arithmetic buss; register selection means responsive to certain first ones of said instruction signals for selecting at least one of (1) a register to provide signals to said origin buss, (2) a register to provide signals to said destination buss, or (3) at least one register which responds to the signals on said arithmetic buss; one of said registers further having associated therewith logic means responsive to certain second ones of said instruction signals appearing on said memory buss to affect the condition of said register and responsive to certain other of said instruction signals to provide signals to said read-only memory means indicating the condition of said one register.

Claim 3

The invention according to claim 1 wherein said read-only memory means includes means responsive to certain of the signals provided to said read-only memory means by said one register for affecting the sequence of the instruction signals provided by said read-only memory means.

Claim 4

The invention according to claim 2: wherein said signal is provided to said read-only memory from said one register through a memory response buss; and wherein said register selection means provides a signal to said read-only memory means through said memory response buss.

Claim 5

The invention according to claim 1 wherein said one register is always selected along with another one of said registers to be responsive to the signal appearing on said arithmetic buss for selected ones of said certain first instruction signals.

Claim 6

The invention according to claim 4 wherein said processor further includes an adder/subtractor means which responds to the occurrence of any one of said selected ones of said certain first instruction signals, in such a manner that any signals caused to appear on at least one of said origin buss or said destination buss are processed thereby in a predetermined manner in accordance with which particular one of said selected certain first instruction signals occurs, said adder/subtractor means thereafter providing a signal to said arithmetic buss.

Claim 7

The invention according to claim 5: wherein said register selection means and said adder/subtractor means respond to a first one of said selected ones of said certain first instruction signals to cause information signals to be applied from a selected origin register through said origin buss to said adder/subtractor means and from a selected destination register through said destination buss to said adder/subtractor means, said adder/subtractor means adding the information manifested by the origin buss and destination buss signals and applying a signal manifesting the added information through said arithmetic buss to said register selected to be responsive to said arithmetic buss signal and to said one register; wherein said register selection means and said adder/subtractor means respond to a second one of said selected ones of said first instruction signals to cause information signals to be applied from a selected origin register through said origin buss to said adder/subtractor means and from a selected destination register through said destination buss to said adder/subtractor means, said adder/subtractor means subtracting the information manifested by the signal appearing on said origin buss from the information manifested by the signal appearing on said destination buss and applying a signal manifesting the subtracted information through said arithmetic buss to said register selected to be responsive to said arithmetic buss signal and to said one register; and wherein said register selection means and said adder/subtractor means respond to a third one of said selected ones of said instruction signals to cause information signals to be applied from a selected origin register through said origin buss to said adder/subtractor means, said adder/subtractor means causing a signal manifesting the same information to be applied through said arithmetic buss to a register selected to be responsive to said arithmetic buss signal and to said one register.

Claim 8

The invention according to claim 6: wherein said first, second, and third ones of said selected first instructions include codes designating the operation to be performed in response to the instruction being provided, which register is to be selected as a destination register to apply a signal to said destination buss and which register is to be selected as an origin register to apply a signal to said origin buss and to be responsive to the signal appearing on said arithmetic buss; wherein said register selection means selects said origin and destination registers according to the codes which designate the registers to be selected as origin and destination of said instruction then being provided in the event said codes are not respectively a first certain number, including zero, and a second certain number, including zero, and performs the operation designated by the code designating said operation; and wherein said register selection means selects said origin and destination registers according to a code stored by said one register in the event the codes of said instruction then being provided which designate said origin and destination registers are respectively said first and second certain numbers, and performs the operation designated by the code designating said operation to be performed.

Claim 9

The invention according to claim 6: wherein each of said selectable registers includes at least one stage, each of said stages being capable of storing a character of information; and wherein said signal applied to said destination buss from said selected destination register manifests the character stored in the most significant stage thereof, said information applied to said origin buss from said selected origin registers manifests the character stored in the most significant stage thereof, all other characters in said selected registers being increased one stage in significance.

Claim 10

The invention according to claim 8 wherein the signal manifesting information applied tO said origin buss from said selected origin register is also applied to the least significant stage of said origin register to cause that information to be stored therein.

Claim 11

The invention according to claim 1: wherein each of said selectable registers includes at least one stage, each of said stages being capable of storing a character of information; wherein one of said instructions has first, second, and third portions which respectively convey information concerning an operation code, a register selection code, and a constant number code; wherein, in the event neither said register selection code or said constant number code is respectively a second certain number, including zero, or a third certain number, including zero, said register selection means responds to said operation code portion of said one instruction by selecting a register according to the register selection code portion of said one instruction and by causing the characters stored by said selected register to be circularly shifted a number of character positions specified by the constant number code of said one instruction; wherein, in the event said constant number coded portion of said one instruction manifests a first certain number, said register selection means responds to said operation code of said one instruction by selecting a register according to the register selection code of said instruction and clearing said selected register; and wherein, in the event said register selection code of said one instruction manifests said second certain number and said constant number code of said one instruction manifests said third certain number, said register selection means responds to said operation code of said one instruction by selecting a register according to a code stored in said one register and circularly shifting the characters in said selected register a given number determined by another code stored in said one register.

Claim 12

A digital processor comprising: a memory buss; a memory response buss; an arithmetic buss; an origin buss; a destination buss; read-only memory means for providing a serial sequence of coded instruction signals in a serial-by-bit manner to said memory buss; a plurality of storage registers each of which can assume a condition manifesting the storage thereby of at least one coded character of information, each of said registers being capable of being selected to provide a signal manifesting a stored character of information in a serial-by-bit manner to at least one of either said origin buss or said destination buss, each of said registers further being capable of being selected to respond to a signal appearing on said arithmetic buss; register selection means coupled to said memory buss, said memory response buss, said arithmetic buss, said origin buss, and said destination buss and responsive to first certain ones of said coded instruction signals appearing on said memory buss for selecting at least one of (1) a register to provide a signal to said origin buss, (2) a register to provide a signal to said destination buss, and (3) a register to respond to signals appearing on said arithmetic buss to store the character manifested by said arithmetic buss signal; operating means coupled to said origin, destination, and arithmetic busses and to said register selection means for operating on signals appearing on said origin and destination busses in a manner determined by the response of said register selection means to an instruction signal and to apply a signal indicative of the results of the operation performed to said arithmetic buss; and accumulator register means coupled to said memory buss, said memory response buss, said origin buss, said destination buss, and said arithmetic buss, and to said register selection means for storing at least one coded character of information, said accumulator register means capable of being selected by said register selection means, Said accumulator register means further being responsive to second certain ones of said coded instruction signals in a manner (1) to affect the coded condition of said character stored thereby or (2) to apply a signal through said memory response buss to said read-only memory means indicating the coded condition of said character stored thereby, said read-only memory means responding to said signal applied thereto from said accumulator register means to affect the sequence of said instruction signals provided thereby.

Claim 13

A digital processor comprising: a memory buss; a memory response buss; an arithmetic buss; an origin buss; a destination buss; read-only memory means for providing a serial sequence of coded instruction signals in a serial-by-bit manner to said memory buss; a plurality of storage registers each of which can assume a condition manifesting the storage thereby of at least one coded character of information, each of said registers being capable of being selected to provide a signal manifesting a stored character of information in a serial-by-bit manner to at least one of either said origin buss or said destination buss, each of said registers further being capable of being selected to respond to a signal appearing on said arithmetic buss; register selection means coupled to said memory buss, said memory response buss, said arithmetic buss, said origin buss, and said destination buss and responsive to first certain ones of said coded instruction signals appearing on said memory buss for selecting at least one of (1) a register to provide a signal to said origin buss, (2) a register to provide a signal to said destination buss, and (3) a register to respond to signals appearing on said arithmetic buss to store the character manifested by said arithmetic buss signal; operating means coupled to said origin, destination, and arithmetic busses and to said register selection means for operating on signals appearing on said origin and destination busses in a manner determined by the response of said register selection means to an instruction signal and to apply a signal indicative of the results of the operation performed to said arithmetic buss; and accumulator register means coupled to said memory buss, said memory response buss, said origin buss, said destination buss, and said arithmetic buss, and to said register selection means for storing at least one coded character of information, said accumulator register means capable of being selected by said register selection means, Said accumulator register means further being responsive to second certain ones of said coded instruction signals in a manner (1) to affect the coded condition of said character stored thereby or (2) to apply a signal through said memory response buss to said read-only memory means indicating the coded condition of said character stored thereby, said read-only memory means responding to said signal applied thereto from said accumulator register means to affect the sequence of said instruction signals provided thereby.

Claim 14

The invention according to claim 11 wherein said accumulator register means is selected to be responsive to a signal appearing on said arithmetic buss and to store the character manifested by that signal whenever one of said storage registers is selected to be responsive to said signal appearing on said arithmetic buss.

Claim 15

The invention according to claim 11: wherein said second certain ones of said instruction signals each have first and second coded portions which respectively manifest an operation to be performed and a constant number associated with said operation to be performed; wherein said second certain instruction signals, which have a first coded portion manifesting that the operation to be performed is to affect the coded condition of the character stored by said accumulator register means include instructions for causing (1) the constant number of said second portion to be stored by said accumulator register means, (2) the logical AND result of said constant number and said stored character to replace said stored character, and (3) the logical OR result of said constant number and said stored character to replace said stored character; and wherein said second certain instruction signals which have a first coded portion manifesting that a signal is to be applied to said read-only memory means indicating the coded condition of said character stored in said accumulator register means include instructions for causing said signal to be applied in the event (1) the stored character and the coded constant portion of said instruction signal are the same, or (2) the stored character has a logical bit of one type in each bit position that said constant has a logical bit of one type.

Claim 16

The invention according to claim 13: wherein signals are applied to said memory response buss after said operating means has completed operating on the signals applied thereto and after said accumulator means has affected the condition of its stored character; wherein said read-only memory means is inhibited from providing another instruction signal until at least after a signal is applied to said memory response buss; and wherein the signals applied to said memory response buss convey different meanings depending upon the time during which they are applied thereto.

Claim 17

A digital processor comprising: read-only memory means having a plurality of multibit storage locations, there being a multibit coded instruction stored in each of said locations, said read-only memory means being responsive to a coded location selection signal which is applied thereto to provide a signal manifesting the coded information stored in a then selected location thereof, the code of said location selection signal determining said then selected location; address control means including a counter which can have the count thereof changed by an incremental amount or a nonincremental amount, said address control means providing said location selection signal to said read-only memory means, the code of said location selection signal being a function of the then existing count of said counter, said address control means being capable of providing an address signal manifesting a function of the then existing count in said counter in response to a first one of said read-only memory signals being applied thereto, said first read-only memory signal causing the count in said counter to be nonincrementAlly changed; and return address register means responsive to said first read-only memory signal capable of performing at least one of (1) storing information which is a function of the address manifested by said address signal in response to an address signal applied thereto from said address control means, and (2) providing a return address signal which manifests the information being stored thereby to said address control means, said return address signal causing the count in said counter to nonincrementally change to a value which is a function of the information manifested by said return address signal.

Claim 18

A digital processor comprising: read-only memory means having a plurality of multibit storage locations, there being a multibit coded instruction stored in each of said locations, said read-only memory means being responsive to a coded location selection signal which is applied thereto to provide a signal manifesting the coded information stored in a then selected location thereof, the code of said location selection signal determining said then selected location; address control means including a counter which can have the count thereof changed by an incremental amount or a nonincremental amount, said address control means providing said location selection signal to said read-only memory means, the code of said location selection signal being a function of the then existing count of said counter, said address control means being capable of providing an address signal manifesting a function of the then existing count in said counter in response to a first one of said read-only memory signals being applied thereto, said first read-only memory signal causing the count in said counter to be nonincrementAlly changed; and return address register means responsive to said first read-only memory signal capable of performing at least one of (1) storing information which is a function of the address manifested by said address signal in response to an address signal applied thereto from said address control means, and (2) providing a return address signal which manifests the information being stored thereby to said address control means, said return address signal causing the count in said counter to nonincrementally change to a value which is a function of the information manifested by said return address signal.

Claim 19

The invention according to claim 15: wherein said first read-only memory signal includes, as a portion thereof, coded information manifesting a constant value, including zero; and wherein said address control means is responsive to said first read-only memory signal to cause the count in said counter to change to a value which is the information manifested by said return address signal as modified by said constant value.

Claim 20

The invention according to claim 15: wherein said first read-only memory signal causes said address signal to be provided by said address control means, said return address register means responding to said address signal by storing the information manifested by said address signal; an wherein the count in said counter is nonincrementally changed to a count manifested by the next sequential read-only memory signal.

Claim 21

The invention according to claim 15 wherein said first read-only memory signal causes said address signal to be provided by said address control means and causes said address control means to be responsive to said return address signal to cause the count in said counter to change to a value which is manifested by said return address signal.

Claim 22

The invention according to claim 18: wherein said first read-only memory signal includes, as a portion thereof, a coded constant number, including zero; and wherein said counter changes its count to a value manifested by said return address signal, as modified by said constant number.

Claim 23

The invention according to claim 15 wherein said address control means is responsive to a said read-only memory signal, which includes, as a portion thereof, information manifesting a constant number, including zero, for causing the count of said counter to be modified by said constant number.

Claim 24

A digital processor capable of having connected thereto a plurality of peripheral units each of which can apply signals to or receive signals from said digital processor comprising: a memory buss, a memory response buss, an arithmetic buss, an origin buss, and a destination buss, each of said busses being capable of coupling a serial-by-bit signal from one selected point in said digital processor to another selected point in said digital processor; read-only memory means for providing instruction signals to said memory buss in response to instruction selection signals applied thereto; instruction selection means responsive to signals applied thereto from said memory buss and said memory response buss for providing said instruction selection signals to said read-only memory; a plurality of selectable storage registers each of which includes at least one stage in which a multibit digital character can be stored, each of said selectable storage registers being connected to said origin buss, said destination buss, and said arithmetic buss, each of said selectable registers being capable of being selected to apply a signal manifesting the character stored in the most significant stage thereof to one of either said origin buss or said destination buss, and when selected to apply a signal to said destination buss to store, as the least significant character thereof, the information manifested by the signal appearing on said arithmetic buss; input/output means coupled to said memory buss, said memory response buss, said arithmetic buss, said origin buss, and said destination buss, including logic means responsive to said instruction signal capable of either applying signals to a selected one of said peripheral units or receiving signals from a selected one of said peripheral units, said selected peripheral unit being selected by said logic means responding to said instruction signal, said signal applied to said selected peripheral unit being determined by at least one of the response of said logic means to said instruction signal or said input/output means being selected to be responsive to the signal appearing on said arithmetic buss, said signal applied to said input/output means by said selected peripheral unit being either compared with a signal derived from said logic means response to said instruction signal or being applied to one of said origin or destination busses, in the event said signal applied to said input/output means is compared with said signal derived from said logic means response to said instruction signal, said logic means applying either a signal to said memory response buss indicating the results of the comparison or a signal, derived from said logic means responding to said instruction signal, to said selected peripheral unit; and operating means responsive to said instruction signal for selecting at least one of which selectable storage register is to apply signals to said origin buss, which selectable register is to apply signals to said destination buss, whether said input/output means is to be selected to apply a signal to said origin buss or said destination buss, or whether said input/output means is to be selected to be responsive to a signal appearing on said arithmetic buss, said operating means further being responsive to any signals appearing on said origin buss and said destination buss to apply a signal to said arithmetic buss after operating on said signals in accordance with a logical response to said instruction signal.

Claim 25

A digital processor capable of having connected thereto a plurality of peripheral units each of which can apply signals to or receive signals from said digital processor comprising: a memory buss, a memory response buss, an arithmetic buss, an origin buss, and a destination buss, each of said busses being capable of coupling a serial-by-bit signal from one selected point in said digital processor to another selected point in said digital processor; read-only memory means for providing instruction signals to said memory buss in response to instruction selection signals applied thereto; instruction selection means responsive to signals applied thereto from said memory buss and said memory response buss for providing said instruction selection signals to said read-only memory; a plurality of selectable storage registers each of which includes at least one stage in which a multibit digital character can be stored, each of said selectable storage registers being connected to said origin buss, said destination buss, and said arithmetic buss, each of said selectable registers being capable of being selected to apply a signal manifesting the character stored in the most significant stage thereof to one of either said origin buss or said destination buss, and when selected to apply a signal to said destination buss to store, as the least significant character thereof, the information manifested by the signal appearing on said arithmetic buss; input/output means coupled to said memory buss, said memory response buss, said arithmetic buss, said origin buss, and said destination buss, including logic means responsive to said instruction signal capable of either applying signals to a selected one of said peripheral units or receiving signals from a selected one of said peripheral units, said selected peripheral unit being selected by said logic means responding to said instruction signal, said signal applied to said selected peripheral unit being determined by at least one of the response of said logic means to said instruction signal or said input/output means being selected to be responsive to the signal appearing on said arithmetic buss, said signal applied to said input/output means by said selected peripheral unit being either compared with a signal derived from said logic means response to said instruction signal or being applied to one of said origin or destination busses, in the event said signal applied to said input/output means is compared with said signal derived from said logic means response to said instruction signal, said logic means applying either a signal to said memory response buss indicating the results of the comparison or a signal, derived from said logic means responding to said instruction signal, to said selected peripheral unit; and operating means responsive to said instruction signal for selecting at least one of which selectable storage register is to apply signals to said origin buss, which selectable register is to apply signals to said destination buss, whether said input/output means is to be selected to apply a signal to said origin buss or said destination buss, or whether said input/output means is to be selected to be responsive to a signal appearing on said arithmetic buss, said operating means further being responsive to any signals appearing on said origin buss and said destination buss to apply a signal to said arithmetic buss after operating on said signals in accordance with a logical response to said instruction signal.

Claim 26

The invention according to claim 21 wherein said instruction signal appearing on said memory buss which causes said input/output means logic to respond thereto is one of a first or a second type, said first type including coded information manifesting the type of instruction, a peripheral unit to be selected, and a signal to be applied to said peripheral unit, said second type of instruction including coded information manifesting the type of the instruction, a peripheral unit to be selected, a code to be compared with the code manifested by a signal applied to said input/output means from the selected peripheral unit, a subinstruction code manifesting action required as a result of the comparison to be made, a code manifesting a signal to be sent to said peripheral unit for certain of said subinstruction codes when the comparison to be made is one result and a code manifesting a constant value which causes said instruction selection means to affect the instruction selection signal applied to said read-only memory means for said certain subinstruction codes where said comparison to be made is another result and where other of said subinstruction codes occur and the comparison to be made is one result.

Claim 27

The invention according to claim 22: wherein said digital processor further includes an accumulator means which can be selected to apply a signal to either said origin buss or said destination buss manifesting a character of information stored thereby; and wherein said input/output means further is responsive to the provision of a third type of instruction signal on said memory buss for causing the logic means thereof to lock one peripheral unit thereto and perform any subsequent instruction signals with respect to said one peripheral unit regardless of any code manifesting a peripheral unit to be selected, said one peripheral unit being determined by said logic means response to a signal manifesting the code of the character stored in said accumulator means.

Claim 28

A digital processor comprising: memory means for prOviding a sequence of serial by bit coded memory signals in response to the code of a program control signal applied thereto; program control means for providing a coded program control signal in which the code thereof may be nonincrementally changed upon command of a branch signal; logic means responsive to said coded memory signals for performing a logical operation and providing one of a series of signals, each signal of said series of signals occurring at a different time, one of said series of signals being said branch signal; and coupling means for coupling said logic means signal to said program control means, said program control means, in response to said branch signal nonincrementally changing the code of said program control signal.

Claim 29

A digital processor comprising: memory means for prOviding a sequence of serial by bit coded memory signals in response to the code of a program control signal applied thereto; program control means for providing a coded program control signal in which the code thereof may be nonincrementally changed upon command of a branch signal; logic means responsive to said coded memory signals for performing a logical operation and providing one of a series of signals, each signal of said series of signals occurring at a different time, one of said series of signals being said branch signal; and coupling means for coupling said logic means signal to said program control means, said program control means, in response to said branch signal nonincrementally changing the code of said program control signal.

Claim 30

The invention according to claim 24 wherein the code of said program control signal is changed in accordance with said sequence of coded memory signals whenever said branch signal is provided by said logic means.

Claim 31

The invention according to claim 24 wherein said logic means signals are pulse signals occurring at specified times and the response of said program control means to nonincrementally change the code of said program control signal occurs when said branch signal occurs at a first specified time.

Claim 32

The invention according to claim 30: wherein said memory means stores a plurality of multibit digital words in sequentially ordered locations each of which are defined by the code of said program control signal; and wherein said program control means includes additional means coupled to said logic means and responsive to said logic means signal for identifying a word read from said memory means as being an instruction word to which said logic means is to respond or a branch word to which said program control means is to nonincrementally change the code of said program control signal, said additional means identifying said word read from said memory means in accordance with the time said logic means signal occurs.

Claim 33

The invention according to claim 27 wherein said logic means includes test register means which stores a given multibit digital word, said test register means being responsive to one of said instruction words that includes a multibit digital constant to determine if said given word has a certain relationship with said constant, said test register means providing a signal to said coupling means during a first given time whenever said certain relationship exists and providing a signal to said coupling means during a second given time whenever said certain relationship does not exist, said program control means responding to said test register means signal which occurs during said first given time by reading the next sequential word from said memory and causing said next sequential word to become the code of said following program control signal, said additional means identifying said next sequential word as being a branch word.

Claim 34

The invention according to claim 28 wherein said program control means includes means for ignoring said next sequential word in the event said test register means signal occurs during said second given time and reads the word following said next sequential word, said additional means including means for identifying said word following said next sequential word as an instruction word.

Claim 35

The invention according to claim 29 wherein said logic means includes other means which stores a multibit digital signal and responds to a two word instruction signal which includes a special coded portion in each word thereof, said other means responding to said first word by providing said logic signal to said coupling means during a third time and by determining whether the special coded portion of said first word is identical to the stored multibit signal, said program control means responding to said logic means signal occurring during said third time to cause the next sequentially ordered word to be read and not treated as an instruction signal, said loGic means responding to said second word by providing said logic means signal to said coupling means during a fourth time in the event said determination was one way and providing said logic means signal to said coupling means during a fifth time in the event said determination was another way, said program control means responding to said logic means signal provided during said fourth time by altering the code of said program control signal by an amount determined by the special coded portion of said second word and said program control means responding to said logic means signal provided during said fifth time by incrementing by one the code of said program control signal.

Claim 36

The invention according to claim 30 wherein said fourth time occurs prior to the time said special coded portion of said second word is serially provided by said memory means.