General purpose digital computer

Claim 1

In a general purpose stored program computer the combination comprising: a random access memory having a first portion which includes a first plurality of individually addressable storage locations for storing information signals in representation of at least one computing program and including operands and instructions for execution of the program, said memory having a second portion which includes a second plurality of individually aDdressable storage locations for storing information signals and having access speed faster than the speed for access to the locations of the first plurality, a location of the second plurality being individually addressable by a block selector code and an in-block code; memory access control means for receiving memory addressing signals and providing access to the locations of the first plurality to withdraw the content of and/or load the same or a new content into the accessed location; program means including the memory access control means and operating to withdraw a sequence of instruction signals from the memory in representation of the program and including means for receiving signals representing individual instructions of the sequence, the means for receiving instruction signals having a plurality of sections of different operative significance and including first, second and third sections and a section for holding an operate code of an instruction signal, at least some of the instruction signals as received by the means for receiving instruction signals from memory by operation of the program means including, for each instruction, two in-block codes set, respectively, into the first and second section, and an operand addressing code set into the third section for serving as operand memory addressing signal for the memory access control means; processor means responsive to the operate code held in the operate code section of the means for receiving instruction signals, to provide instruction execution operations including operations for at least some of the instructions requiring operands held in locations in either or both portions of the memory and including operations which for some of the instructions require participation of an accumulator, source and/or destination registers for information signals; a block selector register providing a block selector code signal and connected to said second portion of the memory for rendering a block of the second plurality storage locations available as general purpose register, accumulator and index register to the exclusion of the remaining locations of the second plurality not included in the block as selected by the current block selector code held in said block selector register; first means connected to be responsive to the in-block code in the first particular section of the means for receiving instruction signals, to access a location of the selected block and to combine the content thereof with the operand addressing code held in the third particular section of the instruction register, and providing an indexed operand address as addressing signals to said memory access control means, for at least some of the instructions in the program; second means connected to be responsive to the in-block code held as content in the second particular section in the means for receiving instruction signals, to access a location in the selected block and being operative for at least some instructions of the program, the accessed location to serve as accumulator or general register, the second means operating concurrently with operation of the access control means for the same instruction; and means included in the processor means and responsive to at least one particular instruction operate code and connected to the block selector register to change the block selector code signal therein.