Modular remote control and supervisory system switchgear

Claim 2

A switchgear comprising a plurality of switching units including command devices, switching devices and signalling devices combined to effect predetermined switching functions, each of the command devices and the switching devices including transmitters for delivering command signals in response to required operating conditions of said devices, each of the switching devices and signalling devices including receivers for receiving command signals, said receivers including storage means for storing the received signals and evaluation means for evaluating the stored signals, a central unit for producing address signals in cyclic sequence, the same address signal being assigned to functionally correlated transmitters and receivers, and a control cable interconnecting a plurality of said transmitters and receivers and connecting said plurality of transmitters and receivers to said central unit, each of said transmitters and receivers being responsive to a definite address signal produced by said central unit, said central unit comprising a signal generator for producing read-out signals of shorter duration than the duration of the address signal, a readout Conductor connecting the output of the read-out signal generator to said receivers of the switchgear, each receiver comprising switching members adapted to release the receiver for the reception of a command signal only when it simultaneously receives the signals of its address and a read-out signal, and a gate circuit connected between, the output of said read-out signal generator and the read-out conductor, said gate circuit having control inputs connected to the outputs of a transmittercontrol circuit and of a receiver-control circuit, in order to block the passage of the read-out signals through the gate circuit when its control circuit receives a blocking signal from the transmitter-control circuit and/or from the receiver-control circuit.

Claim 3

A switchgear according to claim 1, in which each of said transmitters and receivers is adjustable to one of the addresses produced by said central unit.

Claim 4

A switchgear according to claim 1, in which said control cable interconnecting said transmitters and receivers includes a signalling conductor passing through the central unit for amplification of the signals.

Claim 5

A switchgear according to claim 1, in which a plurality of slide-in units are provided containing said command, switching and signalling devices and inserted into shelves of a switch box and connected to mains, each slide-in unit comprising the transmitters and/or receivers for said devices contained therein, and the transmitters and receivers of all slide-in units being connected to a control cable interconnecting said plurality of slide-in units.

Claim 6

A switchgear according to claim 4, in which said control cable passes over the slide-in shelves of said slide box, and each shelf comprises terminal means for connecting the transmitters and receivers of the slide-in unit to be inserted thereon.

Claim 7

A switchgear according to claim 5, in which said terminal means are plug and socket connections.

Claim 8

A switchgear according to claim 3, wherein each slide-in unit comprises exchangeable address units for its transmitters and/or receivers.

Claim 9

A switchgear according to claim 1, in which each of said transmitters supplies command signals in the form of information signals which are complementary to one another, conductors connecting the outputs of the transmitters to the transmitter-control circuit, the transmitter-control circuit being a comparator circuit adapted to deliver a blocking signal to the gate circuit of the read-out signal generator when the received information signals are not complementary.

Claim 10

A switchgear according to claim 8, in which said transmitters produce said command signals in the form of binary signals and each transmitter comprises two separate outputs, one for the direct information signal and one for the inverse information signal of a command signal, said outputs being connected to two separate inputs of the transmitter-control circuit, the transmitter control circuit including means for delivering a blocking signal to the gate circuit of the read-out signal generator when a direct and an inverse information signal are not applied simultaneously at both inputs of the transmitter-control circuit.

Claim 11

A switchgear according to claim 1, in which each of said receivers, upon reception of its address signals, delivers a control signal to a control output, said control outputs of the receivers being connected to the input of the receiver-control circuit so that the latter delivers a blocking signal to the gate circuit of the read-out signal generator when no control signal is present at its input, or when control signals of at least two receivers are not simultaneously present at its input.

Claim 12

A switchgear according to claim 1, in which for the production of read-out signals and address signals consisting of binary signals, the central unit comprises a timing pulse generator and a binary counter connected to the pulse generator, the different stages of said binary counter supplying pulse sequences of successively double periods, a read-out pulse generator being formed by the first stages of the binary counter and by a logical circuit, and each successive stage of the binary counter being connected with an address conductor of said control cable.

Claim 13

A switchgear according to claim 11, in which said logical circuit of the read-out pulse generator comprises a first NAND-gate and a second NAND-gate, each NAND-gate having two inputs, one input of the first NAND-gate being connected to the output of the first stage of said binary counter, and its other input being connected to the output of the second stage of the binary counter, and one input of the second N-AND-gate being connected to the output of the first N-AND-gate and its other input to the output of the third stage of the binary counter, and the output of the second N-AND-gate being connected to the output terminal of the read-out pulse generator.

Claim 14

A switchgear according to claim 10, in which each of said transmitters and each of said receivers comprises a basic circuit having a transistorized decoding circuit for the address signals, the decoding circuit including a n-p-n output transistor whose collector is connected by a first voltage divider to a first terminal for supplying positive operating voltage, and whose emitter is connected to a second terminal for a zero conductor, said output transistor becoming conductive when the decoding circuit receives the signals with the address assigned to it, and said basic circuit including a second n-p-n transistor whose emitter is connected by a first diode with a third terminal, whose collector is connected by a second voltage divider with said first terminal and whose base is connected by a resistor with a fourth terminal and by a further resistor with a fifth terminal, said basic circuit further including a third p-n-p transistor whose emitter is connected to said first terminal for positive operating voltage, whose collector is connected to a sixth terminal and whose base is connected to the center tap of said second voltage divider, and finally the basic circuit including a third p-n-p transistor whose emitter is connected to said first terminal for positive operating voltage, whose collector is connected to a seventh terminal and whose base is connected by a resistor to said first terminal as well as by a Zener-diode, a second diode and a resistor to the collector of said output transistor of the decoding circuit, the collector of said output transistor being connected to an eighth terminal, the center tap of said first voltage divider connected to the emitter of said output transistors, being connected to a ninth terminal, and a tenth terminal being connected by a third diode to the junction point between said second diode and said resistor which is connected to the collector of said output transistor.

Claim 15

A switchgear according to claim 13, in which in said transmitters the eighth terminal, connected to the collector of said output transistor of the decoding circuit, is connected to said third terminal by said first diode which is connected to said first transistor of said basic circuit, said fourth terminal is connected by a resistor to the base of said first transistor, and said fifth terminal, connected by a resistor to the base of said first transistor, is connected to each of two input terminals for supplying the signals denoting the operating condition of the command or switching devices assigned to the respective transmitter, said sixth terminal is connected to the collector of said second transistor of the basic circuit, said tenth terminal connected by said third diode with the junction point between said second diode and a resistor connected to the collector of said output transistor being connected to each other and to a first output terminal which delivers the direct information signal of the command signals, and said seventh terminal, which is connected to the collector of said third transistor of the basic circuit being Connected to a second output terminal which delivers the inverse information signal of the command signals.

Claim 16

A switchgear according to claim 13, in which in said receivers said ninth terminal connected to the center tap of the first voltage divider is connected to said third terminal connected by said first diode to the emitter of said first transistor, the fourth or fifth terminal which are both connected by resistors to the base of said first transistor of the basic circuit is connected to a first input terminal for supplying the transmitter signals, said tenth terminal, which is connected by said third diode with the junction point between the second diode and a resistor connected to the collector of said output transistor, is connected to a second input terminal for supplying the read-out signals, while for furnishing a receiver-control signal, said eighth terminal connected to said output transistor of the decoding circuit is connected by a fourth diode and a resistor series connected therewith, to the receiver-control circuit, said sixth terminal, connected to the collector of said second transistor of the basic circuit and said seventh terminal connected to the collector of said third transistor, being each grounded by a voltage divider and the center taps of the two voltage dividers being connected by a storage and evaluation circuit with output terminals.

Claim 17

A switchgear according to claim 15, in which said storage and evaluation circuit comprises a first N-AND-gate and a second N-AND-gate, one input of both N-AND-gates being connected to the center tap of one of said voltage dividers and the second input of one of the first N-AND-gate being connected to the center tap of the other of said voltage dividers, the output of the first N-AND-gate being connected with the second input of the second N-AND-gate, and the outputs of both N-AND-gates being connected to both inputs of a memory element formed by two N-AND-gates.

Claim 18

A switchgear according to claim 9, in which said transmitter-control circuit consists of an OR gate, and a transistorized matching circuit for the direct and the inverse information signals, is connected to each input of the OR gate.

Claim 19

A switchgear according to claim 1, in which said receiver-control circuit consists of two two-stage amplifiers having each a p-n-p transistor in the first stage and a n-p-n transistor in the second stage, the base of the transistor of the first stage of one of the amplifiers being connected by a Zener-diode with the terminal carrying the positive operating voltage, and being connected to the emitter of the other transistor of the first stage of the other amplifier, the emitter of said other transistor being connected with the input terminal for the receiver-control signals from said receivers, and in each of the two amplifiers the emitter-collector spacing of said n-p-n transistors is bridged by a load resistor and connected to an output terminal.

Claim 20

A switchgear according to claim 11, in which the gate circuit connected to the read-out pulse generator is a N-AND-gate having four inputs, one of which is connected to one output of the receiver-control circuit, a second input to the other output of the receiver-control circuit, a third input to the output of an OR gate of the transmitter-control circuit and the fourth input is connected by a inversion element to the output of said read-out signal generator.