US3700868A — Logical function generator

Claim 1

Independent Claim 258 words

A logical function generator for sequentially generating binary signals in parallel representing the designation numbers for the functions fo, f1, . . . , fk comprising: a continuously recycling input generator means for generating binary signals in parallel representing all of the values of the binary number ao a1 . . . ai during each cycle; switching generator means under the control of said input generating means for generating binary signals in parallel representing all of the values of the binary number xox1 . . . xj with the value of xo x1 . . . xj changing only at the end of each cycle of said input generator means; and circuit generator means receiving the signals representing the values of ao, a1, xo, x1, . . . xj for producing k+1 sequences of binary signals in parallel with each sequence for each cycle of said input generator means representing the designation number of one of the functions fo, f1, . . . fk whereby the values xo, x1, . . . xj define connections for designing logical circuits for generating the logical functions fo, f1, . . . fk; said circuit generating means includes k+1 function generating circuit means with each circuit means receiving the signals representing the values of ao, a1, . . . , ai, fo, f1, . . . fp 1, fp 1, . . . fk and selected ones of the values of xo, x1 . . . , xj for generating the function fp where (p 0, 1, . . . k).

Claim 2

Dependent Claim 258 words

A logical function generator for sequentially generating binary signals in parallel representing the designation numbers for the functions fo, f1, . . . , fk comprising: a continuously recycling input generator means for generating binary signals in parallel representing all of the values of the binary number ao a1 . . . ai during each cycle; switching generator means under the control of said input generating means for generating binary signals in parallel representing all of the values of the binary number xox1 . . . xj with the value of xo x1 . . . xj changing only at the end of each cycle of said input generator means; and circuit generator means receiving the signals representing the values of ao, a1, xo, x1, . . . xj for producing k+1 sequences of binary signals in parallel with each sequence for each cycle of said input generator means representing the designation number of one of the functions fo, f1, . . . fk whereby the values xo, x1, . . . xj define connections for designing logical circuits for generating the logical functions fo, f1, . . . fk; said circuit generating means includes k+1 function generating circuit means with each circuit means receiving the signals representing the values of ao, a1, . . . , ai, fo, f1, . . . fp 1, fp 1, . . . fk and selected ones of the values of xo, x1 . . . , xj for generating the function fp where (p 0, 1, . . . k).

Claim 3

Dependent Claim 42 words

A logical function generator according to claim 1 wherein said switching generator means includes means for constraining the switching generator means such that values of the number xo, x1 . . . xj that do not define useful connections are not generated.

Claim 4

Dependent Claim 52 words

A logical function generator according to claim 1 wherein said input and switching generators each includes a series of flip-flops with the least significant flip-flop of the input generator being driven by a source of clock pulses and with the switching generator driven by the most significant flip-flop of the input generator.

Claim 5

Dependent Claim 125 words

A logical function generator according to claim 1 wherein each of said k+1 function generating circuit means includes three subgroups of logical circuit elements with the first of said subgroups consisting of a single element for producing fp, with the second of said subgroups of logical sircuit elements having their outputs connected to the inputs of said single element, with the third of said subgroups of logical circuit elements having their outputs connected to the inputs of said second subgroups of logical circuit elements and with the ao, a1 . . . a1, xo, x1, . . . xj, fo, f1, . . . fp 1, fp 1 . . . fk values connected to the inputs of said third subgroups of logical circuit elements.

Claim 6

Dependent Claim 87 words

A logical function generator according to claim 4 wherein said third subgroup of logical circuit elements is divided into sub-subgroups with the outputs of each sub-subgroup applied to the inputs of one of the elements in said second subgroup and with the values, ao, a1 . . . ai, fo, f1, . . . fp 1, fp 1, . . . fk and selected ones of the values of xo, x1, . . . xj applied to the inputs of the elements in each of said sub-subgroups.

Claim 7

Dependent Claim 51 words

A logical function generator according to claim 1 including means for storing a binary function g in parallel form and compariNg means for comparing the binary function fp generated by said circuit generator means with g and for producing signal that stops said input and switching generators when any fp g.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1975-10-24	1976-04-24	1976-10-24	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1979-10-24	1980-04-24	1980-10-24	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1983-10-24	1984-04-24	1984-10-24	$7700.00	Window Closed / Lapsed

Logical function generator

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