Arrangement for carrying out alternatively addition or one of a number of logical functions between the contents in a position of two binary words

Claim 2

Arrangement for carrying out alternatively summing or one of a plurality of logical operations between the contents X and Y of a position of two binary words comprising four operand inputs (X, X, Y, Y) to which said binary contents and the complement of said contents, respectively, are supplied, four control inputs (a, b, c, d) the binary condition of which determines one of a maximum of 16 logical operations, a carry bit input (C), a summing determining input (A), a first group of four NAND circuits (G1a, G2b, G3c, G4d), one input of each of said circuits being connected to a different one of said control inputs, respectively, and the other input of each of said circuits being connected via a NOT circuit (G7) to said summing determining input (A), a second group of four NAND circuits (G1, G2, G3, G4), one input of each circuit of said second group being connected to the output of a different NAND circuit of said first group, two other inputs of each circuit of said second group connected to a combination, specific for each circuit, of two operand inputs, one from each word, the fourth input of the two NAND circuits of said second group, to which only complementary or only noncomplementary binary contents are suPplied being connected to said summing determining input via a first further NAND circuit (G5) having one input connected to said carry bit input (C) and a second input connected to said summing determining input (A), a fourth input of the other two NAND circuits (G2, G3) of said second group being connected to the output of a second further NAND circuit (G6), one input of which is connected to said summing determining input (A), and the other input of which is connected to the output of said first further NAND circuit, an AND circuit, the outputs of each NAND circuit of said second group being connected to the inputs of said AND circuit (G8), and the output (S) of said AND circuit being the output of the arrangement.

Claim 3

A logic cell of a arithmetic unit for processing multiposition binary operands wherein the contents of a binary position of two binary operands are alternatively added or logical operated upon to carry out at least one logical function, said cell comprising first, second, third and fourth operand inputs, said first and second operand inputs receiving the contents and the complement of the contents, respectively, of the binary position of one of the two binary operands, said third and fourth operand inputs receiving the contents and the complement of the contents, respectively, of the other of the two binary operands, four NAND circuits, first and second inputs of a first of said NAND circuits being connected to said first and third operand inputs, respectively, first and second inputs of a second of said NAND circuits being connected to said first and four operand inputs, respectively, first and second inputs of a third of said NAND circuits being connected to said second and third operand inputs, respectively, first and second inputs of a fourth of said NAND circuits being connected to a second and fourth operand inputs, respectively, a summing control input adapted to receive a signal to indicate addition, a carry input, a first network of logical elements having first and second inputs and first and second outputs, said first and second inputs of said first network being connected to said summing control input and said carry input, respectively, said first output of said first network being connected to third inputs of said second and third NAND circuits, said second output of said first network being connected to third inputs of said first and fourth NAND circuits, said first logical network controlling said NAND circuits to perform binary addition operations only when a signal is present at said summing control input, a second network of logic elements having a first input connected to said summing control input, at least one other input and at least one output, said other input of said second network being adapted to receive a signal indicating a given logical function and said one output of said second network being connected to a fourth input of at least one of said NAND circuits, said second network controlling said NAND circuits to perform the operation for the given logical function only during the coincidence of the absence of a signal at said summing control input and the presence of the signal indicating the given logical function, and a four-input AND circuit, each input of said AND circuit being connected to the output of a different one of said NAND circuits and the output of said AND circuit being the output of said logic cell.

Claim 4

A logic cell of a arithmetic unit for processing multiposition binary operands wherein the contents of a binary position of two binary operands are alternatively added or logical operated upon to carry out at least one logical function, said cell comprising first, second, third and fourth operand inputs, said first and second operand inputs receiving the contents and the complement of the contents, respectively, of the binary position of one of the two binary operands, said third and fourth operand inputs receiving the contents and the complement of the contents, respectively, of the other of the two binary operands, four NAND circuits, first and second inputs of a first of said NAND circuits being connected to said first and third operand inputs, respectively, first and second inputs of a second of said NAND circuits being connected to said first and four operand inputs, respectively, first and second inputs of a third of said NAND circuits being connected to said second and third operand inputs, respectively, first and second inputs of a fourth of said NAND circuits being connected to a second and fourth operand inputs, respectively, a summing control input adapted to receive a signal to indicate addition, a carry input, a first network of logical elements having first and second inputs and first and second outputs, said first and second inputs of said first network being connected to said summing control input and said carry input, respectively, said first output of said first network being connected to third inputs of said second and third NAND circuits, said second output of said first network being connected to third inputs of said first and fourth NAND circuits, said first logical network controlling said NAND circuits to perform binary addition operations only when a signal is present at said summing control input, a second network of logic elements having a first input connected to said summing control input, at least one other input and at least one output, said other input of said second network being adapted to receive a signal indicating a given logical function and said one output of said second network being connected to a fourth input of at least one of said NAND circuits, said second network controlling said NAND circuits to perform the operation for the given logical function only during the coincidence of the absence of a signal at said summing control input and the presence of the signal indicating the given logical function, and a four-input AND circuit, each input of said AND circuit being connected to the output of a different one of said NAND circuits and the output of said AND circuit being the output of said logic cell.