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Patent US3700865A successfully refreshed from Google Patents.
US3700865A
Expired / Lapsed
US
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Linearizing circuit for frequency domain transducers
Assignee: Gemalto Terminals Ltd
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Filing: 1971-05-07
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Granted: 1972-10-24
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Expires: 1991-05-07
Abstract
Abstract The output of a frequency domain transducer is linearized by converting the output to a mark-space signal which changes level in one sense at each pulse (or each N''the pulse) from the transducer and in the other sense when a fixed number of clock pulses have been counted from the occurrence of the transducer pulse. The mark space signal then operates on an analogue network to effect the linearization by switching the configuration of this network. The analogue network operates either on a fixed analogue signal or an analogue signal representing a second variable when it is desired to multiply the second variable by the first variable transduced by the transducer.
Inventors
- 👤 Anthony John Ley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 10:05
CPC Classifications
H; H03; H03K; H03K7/00; H03K5/00; H03K5/01; H03K5/04; H03K5/05; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
171 words
A circuit for linearizing the output of a frequency domain transducer, comprising an oscillator and a counter arranged to count pulses from the oscillator, means responsive to the transducer output signal to reset the counter to a first predetermined value in response to each N''th pulse from the transducer, where N is 1 or another integer, and means for generating a two level switching waveform which changes from one level to the other in response to each said N''th pulse and back to the one level each time the counter assumes a second predetermined value, the circuit further including a source of an analogue signal and an analogue network operative upon the analogue signal to provide an output analogue signal, the network comprising a plurality of switches controlled by the switching waveform such that the gain of the analogue network switches its value as each switch is switched and the arrangement being such that the mean value of the output analogue signal represents a linearized form of the transducer output signal.
Claim 2
Dependent Claim
171 words
A circuit for linearizing the output of a frequency domain transducer, comprising an oscillator and a counter arranged to count pulses from the oscillator, means responsive to the transducer output signal to reset the counter to a first predetermined value in response to each N''th pulse from the transducer, where N is 1 or another integer, and means for generating a two level switching waveform which changes from one level to the other in response to each said N''th pulse and back to the one level each time the counter assumes a second predetermined value, the circuit further including a source of an analogue signal and an analogue network operative upon the analogue signal to provide an output analogue signal, the network comprising a plurality of switches controlled by the switching waveform such that the gain of the analogue network switches its value as each switch is switched and the arrangement being such that the mean value of the output analogue signal represents a linearized form of the transducer output signal.
Claim 3
Dependent Claim
25 words
A linearizing circuit according to claim 1, wherein said switching waveform and the complement thereof are generated and control different switches in the analogue network.
Claim 4
Dependent Claim
75 words
A linearizing circuit according to claim 1, wherein N is 2 or a multiple thereof and the said generating means generate two switching waveforms of which one changes to its other level every N''th pulse while the second changes to its other level every intervening N''th pulse, both waveforms changing back to their one levels each time the counter assumes the second predetermined value, the two switching waveforms controlling different switches in the analogue network.
Claim 5
Dependent Claim
16 words
A linearizing circuit to claim 1 wherein said analogue network includes at least one chopper switch.
Claim 6
Dependent Claim
23 words
A linearizing circuit according to claim 1 wherein said analogue network includes at least one integrator and a switch for discharging the integrator.
Claim 7
Dependent Claim
17 words
A linearizing circuit according to claim 1 wherein said input analogue signal is a fixed reference value.
Claim 8
Dependent Claim
20 words
A linearizing circuit according to claim 6 and including means for converting the output analogue signal to a markspace signal.
Claim 9
Dependent Claim
85 words
A linearizing circuit according to claim 7 wherein said means for converting comprises an integrator for integrating the output analogue signal, a trigger circuit responsive to the arrival of the output of the Integrator at a predetermined level to enter a SET state for feeding a further signal into the integrator in opposition to the output analogue signal so long as the trigger circuit is SET to cause the trigger circuit to reset, the further signal being derived from the said fixed reference value signal.
Claim 10
Dependent Claim
18 words
A linearizing circuit according to claim 1 wherein said input analogue signal is proportional to a second variable.
Claim 11
Dependent Claim
24 words
A linearizing circuit according to claim 9, wherein said transducer is a density transducer and the input analogue signal is derived from a flowmeter.
Claim 12
Dependent Claim
47 words
A linearizing circuit according to claim 7, further comprising a gate controlled by the mark space signal and a flowmeter feeding pulses whose rate is proportional to volumetric flow rate to the gate to be passed thereby when the gate is enabled by the mark space signal.
References Cited (Backward Citations)
US3610898A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-24 | 1976-04-24 | 1976-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-24 | 1980-04-24 | 1980-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-24 | 1984-04-24 | 1984-10-24 | $7700.00 | Window Closed / Lapsed |