Patent US3699467A successfully refreshed from Google Patents.
US3699467A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bias circuit for a complementary transistor output stage
Assignee: RCA Licensing Corp
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Filing: 1969-12-29
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Granted: 1972-10-17
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Expires: 1989-12-29
Abstract
Abstract A bias circuit for a complementary transistor power amplifier output stage which comprises a biasing transistor having its emitter connected to the base of one of the complementary transistors and its collector connected to the base of the other of the complementary transistors. A collector resistor is in circuit with the collector of the biasing transistor and with a source of biasing potential. The input signal to the amplifier is coupled to the emitter of the biasing transistor and to the base of one of the complementary transistors. In one embodiment, a resistive divider biases the base of the biasing transistor, while in another embodiment, the base of the biasing transistor is directly connected to the source of biasing potential.
Inventors
- 👤 Stephen Grout
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:54
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/30; H03F3/3069; H03F3/3071
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
159 words
A bias circuit for an amplifier wherein said bias circuit comprises: a. connecting means for connecting said bias circuit to a source of biasing potential; b. a bias transistor having a base, a collector and an emitter, said bias transistor developing a bias voltage for said amplifier between said emitter and collector, and said bias transistor being coupled at its collector and its emitter to said amplifier to apply said bias voltage to said amplifier; c. means for applying an input signal to said bias transistor at its emitter; d. feedback means, said feedback means including voltage developing means in circuit with said collector, said voltage developing means being responsive to current flow through said collector to develope a voltage across said voltage developing means; and e. means for applying said developed voltage to the base of said bias transistor for maintaining said bias voltage substantially constant over a predetermined range of collector current flow through said bias transistor.
Claim 2
Dependent Claim
159 words
A bias circuit for an amplifier wherein said bias circuit comprises: a. connecting means for connecting said bias circuit to a source of biasing potential; b. a bias transistor having a base, a collector and an emitter, said bias transistor developing a bias voltage for said amplifier between said emitter and collector, and said bias transistor being coupled at its collector and its emitter to said amplifier to apply said bias voltage to said amplifier; c. means for applying an input signal to said bias transistor at its emitter; d. feedback means, said feedback means including voltage developing means in circuit with said collector, said voltage developing means being responsive to current flow through said collector to develope a voltage across said voltage developing means; and e. means for applying said developed voltage to the base of said bias transistor for maintaining said bias voltage substantially constant over a predetermined range of collector current flow through said bias transistor.
Claim 3
Dependent Claim
38 words
A bias circuit as recited in claim 1 wherein said voltage developing means includes means for causing said bias voltage to decrease with increased ambient temperature over said predetermined range of collector current flow through said bias transistor.
Claim 4
Dependent Claim
39 words
A bias circuit as recited in claim 1 wherein said voltage developing means includes means for causing said bias voltage to decrease with an increased collector current over said predetermined range of collector current flow through said bias transistor.
Claim 5
Dependent Claim
54 words
A bias circuit as recited in claim 1 wherein said amplifier comprises a pair of complementary PNP and NPN transistors series coupled emitter to emitter, the NPN transistor coupled at its base to the collector of said bias transistor and the PNP transistor coupled at its base to the emitter of said bias transistor.
Claim 6
Dependent Claim
37 words
A bias circuit as recited in claim 4 wherein said voltage developing means includes a resistive element preselected to maintain said bias voltage substantially constant over said predetermined range of collector current flow through said bias transistor.
Claim 7
Dependent Claim
52 words
A bias circuit as recited in claim 4 wherein said voltage developing means includes a resistive element preselected to cause said bias voltage to decrease as the emitter current of each of said complementary transistors increases with incrEased ambient temperature over said predetermined range of collector current flow through said bias transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-17 | 1976-04-17 | 1976-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-17 | 1980-04-17 | 1980-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-17 | 1984-04-17 | 1984-10-17 | $7700.00 | Window Closed / Lapsed |