Patent US3698007A successfully refreshed from Google Patents.
US3698007A
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Central processor unit having simulative interpretation capability
Assignee: Honeywell Inc
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Filing: 1970-11-30
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Granted: 1972-10-10
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Expires: 1990-11-30
Abstract
Abstract An electronic digital computer provides real time simulation of the operation of a different digital computer with a minimal amount of special interpretive software. The central processor of the simulating computer develops and stores in one register the memory address of the operands processed by the program being interpreted. In another register, the simulating processor develops and stores the memory address of an interpretive subroutine for each instruction of the program being interpreted. The simulating computer in addition operates a third central processor register as an effective program counter during execution of simulative interpretation. A fourth register is used to supply the memory sector portion of the memory addresses developed above. Each of the four registers is directly accessible by other elements of the central processor.
Inventors
- 👤 Ronald D Malcolm
- 👤 William J Phelan
- 👤 Thomas L Sangiolo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 07:45
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/455; G06F9/45504
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
309 words
A method of simulating in real time the operation of a general purpose source computer on another general purpose computer including a first, second, third, fourth and fifth register means operable to receive and temporarily store information and to transfer information with respect to each other and to other elements of the processor unit and including op-code register means comprising the steps of: a. storing in an allocated section of computer memory source program (S) instructions; b. storing in another section of computer memory source program (S) operands; c. storing in still another section of computer memory interpretive subroutine instructions by which the (S) instructions are interpreted into the language of the modified computer; d. storing in first temporary storage the sector address in computer memory of the interpretive subroutine instructions and the (S) program operands; e. storing in second temporary storage the starting address of (S) program instructions; f. fetching from computer memory a source program (S) instruction having (S) op-code and index bits and temporarily storing it in third temporary storage; g. forming, in fourth temporary storage, the address of source (S) program operands by, 1. transferring from first temporary storage into fourth temporary storage the sector address of source program (S) operands, and also 2. transferring from third temporary storage into fourth temporary storage the index bits of the source program (S) instruction; h. forming in fifth temporary storage the address of an interpretive subroutine instruction by, 1. transferring from first temporary storage into fifth temporary storage the sector address of the interpretive subroutine instructions, and also 2. transferring from third temporary storage into fifth temporary storage the op-code bits of the source program (S) instruction; i. and fetching from computer memory the subroutine instruction having subroutine op-code and index bits and storing it in third temporary storage in place of the source program (S) instruction.
Claim 2
Independent Claim
309 words
A method of simulating in real time the operation of a general purpose source computer on another general purpose computer including a first, second, third, fourth and fifth register means operable to receive and temporarily store information and to transfer information with respect to each other and to other elements of the processor unit and including op-code register means comprising the steps of: a. storing in an allocated section of computer memory source program (S) instructions; b. storing in another section of computer memory source program (S) operands; c. storing in still another section of computer memory interpretive subroutine instructions by which the (S) instructions are interpreted into the language of the modified computer; d. storing in first temporary storage the sector address in computer memory of the interpretive subroutine instructions and the (S) program operands; e. storing in second temporary storage the starting address of (S) program instructions; f. fetching from computer memory a source program (S) instruction having (S) op-code and index bits and temporarily storing it in third temporary storage; g. forming, in fourth temporary storage, the address of source (S) program operands by, 1. transferring from first temporary storage into fourth temporary storage the sector address of source program (S) operands, and also 2. transferring from third temporary storage into fourth temporary storage the index bits of the source program (S) instruction; h. forming in fifth temporary storage the address of an interpretive subroutine instruction by, 1. transferring from first temporary storage into fifth temporary storage the sector address of the interpretive subroutine instructions, and also 2. transferring from third temporary storage into fifth temporary storage the op-code bits of the source program (S) instruction; i. and fetching from computer memory the subroutine instruction having subroutine op-code and index bits and storing it in third temporary storage in place of the source program (S) instruction.
Claim 3
Dependent Claim
32 words
transferring from third temporary storage into fourth temporary storage the index bits of the source program (S) instruction; h. forming in fifth temporary storage the address of an interpretive subroutine instruction by,
Claim 4
Dependent Claim
32 words
transferring from third temporary storage into fourth temporary storage the index bits of the source program (S) instruction; h. forming in fifth temporary storage the address of an interpretive subroutine instruction by,
Claim 5
Dependent Claim
48 words
transferring from third temporary storage into fifth temporary storage the op-code bits of the source program (S) instruction; i. and fetching from computer memory the subroutine instruction having subroutine op-code and index bits and storing it in third temporary storage in place of the source program (S) instruction.
Claim 6
Dependent Claim
48 words
transferring from third temporary storage into fifth temporary storage the op-code bits of the source program (S) instruction; i. and fetching from computer memory the subroutine instruction having subroutine op-code and index bits and storing it in third temporary storage in place of the source program (S) instruction.
Claim 7
Dependent Claim
24 words
The method of claim 1 including the step of storing in computer memory a jump interpretive (JIN) instruction having JIN op-code and index bits.
Claim 8
Dependent Claim
35 words
The method of claim 1 wherein simulative interpretation of the source computer is commenced by further steps comprising fetching a JIN instruction from computer memory and loading the JIN op-code into the op-code register means.
Claim 9
Dependent Claim
34 words
The method of claim 3 including the further step of transferring from third storage means into op-code means the op-code and index bits of the interpretive subroutine instruction in place of the JIN op-code.
Claim 10
Dependent Claim
38 words
The method of claim 4 including the furthEr steps of fetching and executing successive interpretive subroutine instructions by, a. incrementing the interpretive subroutine instruction address formed in fifth temporary storage means after the execution of each subroutine instruction.
Claim 11
Dependent Claim
57 words
The method of claim 5 wherein the termination of fetching and executing one group of successive interpretive sub-routine instructions and commencing the fetching and executing of another group of interpretive sub-routines is signalled by the further step comprising moving a jump interpretive (JIN) instruction into third temporary storage addressed by an incremented address in fifth storage means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-10 | 1976-04-10 | 1976-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-10 | 1980-04-10 | 1980-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-10 | 1984-04-10 | 1984-10-10 | $7700.00 | Window Closed / Lapsed |