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US3697879A
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On-off pulse time control
Assignee: ELTEE PULSITRON
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Filing: 1971-08-31
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Granted: 1972-10-10
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Expires: 1991-08-31
Abstract
Abstract An on-off pulse time control comprising a pulse generator providing a source of time base pulses to on and off timer circuits each of which includes a set of counters for producing a time signal upon completion of a pre-selected time interval. The output of each counter is connected to an inverter gate which provides a logical true signal to a synchronization gate associated with each timer. The outputs of the synchronization gates are applied to a flip flop circuit which resets one timer and simultaneously sets the other timer to initiate its time interval, thus providing a continuous on-off timed cycle.
Inventors
- 👤 Jack D Holliday
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:11
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/78
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
141 words
In combination, a source of recurring electrical pulses timing means comprising first and second counting means for counting said pulses to produce first and second time signals respectively upon completion of first and second preselected time intervals, said first and second counting means each having set and reset states for initiate and terminate counting by said counting means, first and second gate means enabled by completion of said first and second time intervals respectively, and third gate means responsive to the modes of said first and second gate means for providing a reset signal to one of said counting means and a set signal to the other of said counting means upon completion of a preselected time interval of said one counting means, said set signal enabling the other of said counting means to initiate counting of its preselected time interval.
Claim 2
Dependent Claim
141 words
In combination, a source of recurring electrical pulses timing means comprising first and second counting means for counting said pulses to produce first and second time signals respectively upon completion of first and second preselected time intervals, said first and second counting means each having set and reset states for initiate and terminate counting by said counting means, first and second gate means enabled by completion of said first and second time intervals respectively, and third gate means responsive to the modes of said first and second gate means for providing a reset signal to one of said counting means and a set signal to the other of said counting means upon completion of a preselected time interval of said one counting means, said set signal enabling the other of said counting means to initiate counting of its preselected time interval.
Claim 3
Dependent Claim
75 words
The combination set forth in claim 1 wherein said first and second counting means each include a plurality of cascaded binary counters, a decimal decoder connected to each of said binary counters for providing a decimal output equivalent to the binary output of the associated binary counter and bistable gate means associated with each decimal decoder for enabling said first and second gate means when the counters associated therewith have counted the preselected time interval.
Claim 4
Dependent Claim
62 words
The combination set forth in claim 2 wherein said first and second gate means include first and second NAND circuit means respectively each connected to the associated outputs of said bistable gate means, the state of each NAND circuit means being changed only when all of the bistable gate means associated therewith are enabled by the completion of a preselected time interval.
Claim 5
Dependent Claim
73 words
The combination set forth in claim 2 wherein said third gate means includes a bistable flip flop circuit having a first output of one logic mode connected to the decade counters associated with said first timing means and a second output of the opposite logic mode connected to the decade counters associated with said second timing means, the logic mode of the flip flop being effective to set and reset said decade counters.
Claim 6
Dependent Claim
84 words
The combination set forth in claim 4 wherein said first and second gate means include first and second NAND circuit means respectively each connected to the associated outputs of said bistable gate means, the state of each NAND circuit means being changed only when all of the bistable gate means associated therewith are enabled by the completion of a preselected time interval, said NAND change circuit means being effective to change the state of said flip flop circuit upon completion of a time interval.
Claim 7
Dependent Claim
21 words
The combination set forth in claim 5 together with buffer gate means between each flip flop output and said decade counters.
Claim 8
Dependent Claim
118 words
A timer for providing time output signals, said timer comprising a frequency source of recurring time base electrical pulses, timing means comprising first and second settable counting means for counting said pulses to produce first and second time signals respectively upon completion of corresponding preselected time intervals, said first and second counting means each having a reset state for resetting to zero, gate means responsive to the completion of said preselected time intervals for simultaneously resetting one of said counting means upon completion of its count and setting the other of said counting means to initiate its count, and output circuit means connected to said gate means for processing the signals therefrom to provide said timed output signals.
Claim 9
Dependent Claim
118 words
A timer for providing time output signals, said timer comprising a frequency source of recurring time base electrical pulses, timing means comprising first and second settable counting means for counting said pulses to produce first and second time signals respectively upon completion of corresponding preselected time intervals, said first and second counting means each having a reset state for resetting to zero, gate means responsive to the completion of said preselected time intervals for simultaneously resetting one of said counting means upon completion of its count and setting the other of said counting means to initiate its count, and output circuit means connected to said gate means for processing the signals therefrom to provide said timed output signals.
Claim 10
Dependent Claim
35 words
The timer set forth in claim 7 wherein said gate means includes first and second bistable gate means enabled by said first and second counting means respectively upon completion of the associated preselected time interval.
Claim 11
Dependent Claim
65 words
The timer set forth in claim 8 wherein said gate means further includes flip flop circuit means connected to the outputs of first and second bistable gate means and being effective to simultaneously change the states of said bistable counting means in response to a change in state of either said first or second bistable gate means due to the completion of a time interval.
Claim 12
Dependent Claim
50 words
The timer set forth in claim 9 wherein said first and second bistable gate means each include NAND circuit means connected to the outputs of said first and second counting means respectively, the state of said NAND circuit means being changed only by the completion of a preselecTed time interval.
Claim 13
Dependent Claim
34 words
The timer set forth in claim 10 wherein said output circuit includes NAND buffer gate means connected to an inverting and amplifier circuit to provide low impedence timed output signals for driving external circuitry.
Claim 14
Dependent Claim
42 words
The timer set forth in claim 10 wherein said frequency pulse source includes at least two crystals of different resonant frequency to provide corresponding time base pulses, and means for selecting the frequency of time base pulses fed to said timing means.
Claim 15
Dependent Claim
24 words
The timer set forth in claim 10 wherein said pulse source includes a NAND buffer gate connected to an oscillator output of predetermined frequency.
Claim 16
Dependent Claim
24 words
The timer set forth in claim 10 wherein said first and second counting means each include matrix means for control of said time intervals.
Claim 17
Dependent Claim
49 words
The timer set forth in claim 10 wherein said first and second counting means each include a plurality of bistable gates the outputs of which are connected to said NAND circuit means, the state thereof being changed only upon the enablement of all of said bistable gates associated therewith.
References Cited (Backward Citations)
US3388346A
Cited
US3486044A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-10 | 1976-04-10 | 1976-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-10 | 1980-04-10 | 1980-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-10 | 1984-04-10 | 1984-10-10 | $7700.00 | Window Closed / Lapsed |