US3665404A — Multi-processor processing system having interpro…

Claim 1

Independent Claim 373 words

A multi-processor data processing system comprising: 1. memory means for storing program and data words; 2. two interruptable processors for executing sequences of arithmetic and logical operations on digital data, each processor including a. means for executing program instructions for manipulating data in response to control signals, b. means responsive to program words obtained from the memory means for generating control signals which cause the data manipulating means to execute a sequence of program instructions, c. an interrupt handler operable in response to an interrupt command signal for forming control signals which cause the data manipulation means to interrupt the execution of a sequence of program instructions, the interrupt handler while it is operative cooperating with the data manipulation means to execute a supervisory task, d. bistable means having a first state for indicating that its interrupt handler is operative and hence unavailable and having a second state indicating that its interrupt handler is available; e. gating means enabled by the second state and disabled by the first state for supplying the interrupt command signal to the interrupt handler when an interrupt request signal is received only while the interrupt handler is available; 3. an input/output unit for transferring digital words into and out of the processing system; 4. signal generating means for indicating that the input/output unit has assumed a predetermined operating status which requires the attention of a processor to execute a supervisory task; and 5. means for simultaneously assigning to each processor a different initial priority for executing the supervisory tasks required by the input/output unit, a first one of the two processors being assigned initial primary priority and a second one being assigned initial secondary priority; 6. means responsive to the assigning means and the first state of the bistable means in the first processor for producing a transfer signal when the interrupt handler therein is unavailable; and 7. means responsive to the signal generating means, the assigning means, and the transfer signal for providing the interrupt request signal to only the gating means in the first processor when its interrupt handler is available and otherwise to both gating means and thereby causing the processors to share the load of executing the supervisory tasks required by the input/output unit.

Claim 2

Dependent Claim 373 words

A multi-processor data processing system comprising: 1. memory means for storing program and data words; 2. two interruptable processors for executing sequences of arithmetic and logical operations on digital data, each processor including a. means for executing program instructions for manipulating data in response to control signals, b. means responsive to program words obtained from the memory means for generating control signals which cause the data manipulating means to execute a sequence of program instructions, c. an interrupt handler operable in response to an interrupt command signal for forming control signals which cause the data manipulation means to interrupt the execution of a sequence of program instructions, the interrupt handler while it is operative cooperating with the data manipulation means to execute a supervisory task, d. bistable means having a first state for indicating that its interrupt handler is operative and hence unavailable and having a second state indicating that its interrupt handler is available; e. gating means enabled by the second state and disabled by the first state for supplying the interrupt command signal to the interrupt handler when an interrupt request signal is received only while the interrupt handler is available; 3. an input/output unit for transferring digital words into and out of the processing system; 4. signal generating means for indicating that the input/output unit has assumed a predetermined operating status which requires the attention of a processor to execute a supervisory task; and 5. means for simultaneously assigning to each processor a different initial priority for executing the supervisory tasks required by the input/output unit, a first one of the two processors being assigned initial primary priority and a second one being assigned initial secondary priority; 6. means responsive to the assigning means and the first state of the bistable means in the first processor for producing a transfer signal when the interrupt handler therein is unavailable; and 7. means responsive to the signal generating means, the assigning means, and the transfer signal for providing the interrupt request signal to only the gating means in the first processor when its interrupt handler is available and otherwise to both gating means and thereby causing the processors to share the load of executing the supervisory tasks required by the input/output unit.

Claim 3

Dependent Claim 5 words

an interrupt transfer circuit, and

Claim 4

Dependent Claim 5 words

an interrupt transfer circuit, and

Claim 5

Dependent Claim 177 words

two interruptable processors for executing sequences of arithmetic and logical operations on digital data, each processor including a. means for executing program instructions for manipulating data in response to control signals, b. means responsive to program words obtained from the memory means for generating control signals which cause the data manipulating means to execute a sequence of program instructions, c. an interrupt handler operable in response to an interrupt command signal for forming control signals which cause the data manipulation means to interrupt the execution of a sequence of program instructions, the interrupt handler while it is operative cooperating with the data manipulation means to execute a supervisory task, d. bistable means having a first state for indicating that its interrupt handler is operative and hence unavailable and having a second state indicating that its interrupt handler is available; e. gating means enabled by the second state and disabled by the first state for supplying the interrupt command signal to the interrupt handler when an interrupt request signal is received only while the interrupt handler is available;

Claim 6

Dependent Claim 177 words

two interruptable processors for executing sequences of arithmetic and logical operations on digital data, each processor including a. means for executing program instructions for manipulating data in response to control signals, b. means responsive to program words obtained from the memory means for generating control signals which cause the data manipulating means to execute a sequence of program instructions, c. an interrupt handler operable in response to an interrupt command signal for forming control signals which cause the data manipulation means to interrupt the execution of a sequence of program instructions, the interrupt handler while it is operative cooperating with the data manipulation means to execute a supervisory task, d. bistable means having a first state for indicating that its interrupt handler is operative and hence unavailable and having a second state indicating that its interrupt handler is available; e. gating means enabled by the second state and disabled by the first state for supplying the interrupt command signal to the interrupt handler when an interrupt request signal is received only while the interrupt handler is available;

Claim 7

Dependent Claim 154 words

In a programmable data processing system having first and second interrupt handling apparatus each having interruptable and non-interruptable states and each responsive to an interrupt control signal for handling an interrupt, and means for providing a signal requesting an interrupt, the combination comprising: means for simultaneously assigning a primary and a secondary priority in which each of said first and second interrupt handling apparatus is to handle an interrupt; and means responsive to a signal requesting an interrupt for applying an interrupt control signal to one of said first and second interrupt handling apparatus and thereby causing an interrupt, which includes means responsive to the assigning means for applying an interrupt control signal to the interrupt handling apparatus assigned primary priority while it is in its interruptable state and for applying an interrupt control signal to the interrupt handling apparatus assigned secondary priority while the other interrupt handling apparatus is in its interruptable state.

Claim 8

Dependent Claim 154 words

In a programmable data processing system having first and second interrupt handling apparatus each having interruptable and non-interruptable states and each responsive to an interrupt control signal for handling an interrupt, and means for providing a signal requesting an interrupt, the combination comprising: means for simultaneously assigning a primary and a secondary priority in which each of said first and second interrupt handling apparatus is to handle an interrupt; and means responsive to a signal requesting an interrupt for applying an interrupt control signal to one of said first and second interrupt handling apparatus and thereby causing an interrupt, which includes means responsive to the assigning means for applying an interrupt control signal to the interrupt handling apparatus assigned primary priority while it is in its interruptable state and for applying an interrupt control signal to the interrupt handling apparatus assigned secondary priority while the other interrupt handling apparatus is in its interruptable state.

Claim 9

Dependent Claim 158 words

In an interruptable programmable data processing system including at least first and second means each making requests for an interrupt condition to be processed, an interrupt handling system comprising: first and second interrupt handlers, means for simultaneously assigning the first and second interrupt handlers primarily to said first and second means respectively, each handler having an interruptable state in which it can be actuated to process an interrupt; means responsive to the assigning means for selecting for actuation the respective primarily assigned interrupt handler when a request for access is made by either of said first or second means and for actuating such selected interrupt handler in response to its being in its interruptable state; and transfer means for selecting for actuation the other respective interrupt handler, not primarily assigned, when a request for access is made by either one of said first or second means and the interrupt handler primarily assigned thereto is in its non-interruptable state.

Claim 10

Dependent Claim 158 words

In an interruptable programmable data processing system including at least first and second means each making requests for an interrupt condition to be processed, an interrupt handling system comprising: first and second interrupt handlers, means for simultaneously assigning the first and second interrupt handlers primarily to said first and second means respectively, each handler having an interruptable state in which it can be actuated to process an interrupt; means responsive to the assigning means for selecting for actuation the respective primarily assigned interrupt handler when a request for access is made by either of said first or second means and for actuating such selected interrupt handler in response to its being in its interruptable state; and transfer means for selecting for actuation the other respective interrupt handler, not primarily assigned, when a request for access is made by either one of said first or second means and the interrupt handler primarily assigned thereto is in its non-interruptable state.

Claim 11

Dependent Claim 14 words

an input/output unit for transferring digital words into and out of the processing system;

Claim 12

Dependent Claim 14 words

an input/output unit for transferring digital words into and out of the processing system;

Claim 13

Dependent Claim 108 words

a busy indicator for the corresponding interrupt handler; d. means for coupling the interrupt transfer circuits together and to the interrupt handler for the corresponding processor; and e. means for assigning to each processor a priority for attention to the input and/or output units; said transfer circuits comprising means responsive to said priority means, a not busy indication, and a predetermined attention needed signal for activating the interrupt handler for the corresponding processor and responsive to a busy indication for enabling another transfer circuit to respond to the same predetermined attention needed signal and thereby activate the interrupt handler for the processor associated with said another transfer circuit.

Claim 14

Dependent Claim 108 words

a busy indicator for the corresponding interrupt handler; d. means for coupling the interrupt transfer circuits together and to the interrupt handler for the corresponding processor; and e. means for assigning to each processor a priority for attention to the input and/or output units; said transfer circuits comprising means responsive to said priority means, a not busy indication, and a predetermined attention needed signal for activating the interrupt handler for the corresponding processor and responsive to a busy indication for enabling another transfer circuit to respond to the same predetermined attention needed signal and thereby activate the interrupt handler for the processor associated with said another transfer circuit.

Claim 15

Dependent Claim 28 words

signal generating means for indicating that the input/output unit has assumed a predetermined operating status which requires the attention of a processor to execute a supervisory task; and

Claim 16

Dependent Claim 28 words

signal generating means for indicating that the input/output unit has assumed a predetermined operating status which requires the attention of a processor to execute a supervisory task; and

Claim 17

Dependent Claim 54 words

A system according to claim 3 wherein said transfer means comprises first and second gating means, the first gating means selectively coupling a request for access by said first means to said second interrupt handler and said second gating means coupling a request for access by said second means to said first interrupt handler.

Claim 18

Dependent Claim 42 words

means for simultaneously assigning to each processor a different initial priority for executing the supervisory tasks required by the input/output unit, a first one of the two processors being assigned initial primary priority and a second one being assigned initial secondary priority;

Claim 19

Dependent Claim 42 words

means for simultaneously assigning to each processor a different initial priority for executing the supervisory tasks required by the input/output unit, a first one of the two processors being assigned initial primary priority and a second one being assigned initial secondary priority;

Claim 20

Dependent Claim 205 words

In a data processing system having a pair of interruptable processors and an input/output unit, an automatic interrupt handling system comprising: a pair of interrupt handlers for exercising control over data transfer operAtions of the input/output unit while a respective one of the interruptable processors is interrupted, each interrupt handler either being available for exercising such control or being unavailable therefor; means for producing a first signal when the input/output unit assumes a predetermined operating status, the first signal representing a request for the attention of an interrupt handler to exercise such control; means for simultaneously assigning initial primary priority to a first one of the interrupt handlers and initial secondary priority to the other interrupt handler for exercising such control; means for producing a second signal during periods of time in which said first interrupt handler is unavailable; means responsive to the assigning means and the first signal for actuating said first interrupt handler so as to exercise such control when that interrupt handler is available; and means responsive to the coincidence of the first and second signals for providing a third signal to said other interrupt handler to enable that interrupt handler to exercise its control when the first interrupt handler is unavailable.

Claim 21

Dependent Claim 205 words

In a data processing system having a pair of interruptable processors and an input/output unit, an automatic interrupt handling system comprising: a pair of interrupt handlers for exercising control over data transfer operAtions of the input/output unit while a respective one of the interruptable processors is interrupted, each interrupt handler either being available for exercising such control or being unavailable therefor; means for producing a first signal when the input/output unit assumes a predetermined operating status, the first signal representing a request for the attention of an interrupt handler to exercise such control; means for simultaneously assigning initial primary priority to a first one of the interrupt handlers and initial secondary priority to the other interrupt handler for exercising such control; means for producing a second signal during periods of time in which said first interrupt handler is unavailable; means responsive to the assigning means and the first signal for actuating said first interrupt handler so as to exercise such control when that interrupt handler is available; and means responsive to the coincidence of the first and second signals for providing a third signal to said other interrupt handler to enable that interrupt handler to exercise its control when the first interrupt handler is unavailable.

Claim 22

Dependent Claim 31 words

means responsive to the assigning means and the first state of the bistable means in the first processor for producing a transfer signal when the interrupt handler therein is unavailable; and

Claim 23

Dependent Claim 31 words

means responsive to the assigning means and the first state of the bistable means in the first processor for producing a transfer signal when the interrupt handler therein is unavailable; and

Claim 24

Dependent Claim 57 words

The interrupt handling system of claim 5 wherein the priority assigning means comprises a source producing a continuous logical signal and wherein the means for activating the first interrupt handler comprises a gating circuit responsive to the coincidence of the continuous logical signal and the first signal to produce a signal for activating the first interrupt handler.

Claim 25

Dependent Claim 76 words

The interrupt handling system of claim 5 including a memory, the processors being programmatically controlled by object programs and an executive program obtained from the memory, an interrupt handler being provided in each processor and comprising a controllable operator control network responsive to the executive program; and means for simultaneously coupling the first signal to each of the processors so that whichever one of the interrupt handlers is assigned initial primary priority can respond thereto immediately.

Claim 26

Dependent Claim 60 words

means responsive to the signal generating means, the assigning means, and the transfer signal for providing the interrupt request signal to only the gating means in the first processor when its interrupt handler is available and otherwise to both gating means and thereby causing the processors to share the load of executing the supervisory tasks required by the input/output unit.

Claim 27

Dependent Claim 60 words

means responsive to the signal generating means, the assigning means, and the transfer signal for providing the interrupt request signal to only the gating means in the first processor when its interrupt handler is available and otherwise to both gating means and thereby causing the processors to share the load of executing the supervisory tasks required by the input/output unit.

Claim 28

Dependent Claim 247 words

A program controlled data processing system comprising: first and second groups of input/output units for transferring data into and out of the data processing system; first and second signal generating means, each for producing an attention needed signal for a corresponding one of the first and second groups, the attention needed signals indicating that a processor should be interrupted to process a supervisory task relating to the transfer of data; first and second processors associated primarily with the first and second signal generating means respectively; coupling means including means for coupling each processor to each signal generating means for transmitting each attention needed signal so as to be simultaneously received in each processor, and means for coupling the processors together for transmitting transfer signals therebetween; each processor including first means for simultaneously assigning initial primary priority to attention needed signals transmitted thereto from its associated signal generating means and initial secondary priority to attention need signals transmitted thereto from the other signal generating means; second means for indicating whether the processor is available for executing a supervisory task; third means responsive to the second means for applying a transfer signal to the coupling means for transmission to the other processor; and fourth means responsive to the first, second, and third means for executing a supervisory task when available therefor and either an attention needed signal assigned initial primary priority is received or an attention needed signal assigned initial secondary priority and a transfer signal are received simultaneously.

Claim 29

Dependent Claim 247 words

A program controlled data processing system comprising: first and second groups of input/output units for transferring data into and out of the data processing system; first and second signal generating means, each for producing an attention needed signal for a corresponding one of the first and second groups, the attention needed signals indicating that a processor should be interrupted to process a supervisory task relating to the transfer of data; first and second processors associated primarily with the first and second signal generating means respectively; coupling means including means for coupling each processor to each signal generating means for transmitting each attention needed signal so as to be simultaneously received in each processor, and means for coupling the processors together for transmitting transfer signals therebetween; each processor including first means for simultaneously assigning initial primary priority to attention needed signals transmitted thereto from its associated signal generating means and initial secondary priority to attention need signals transmitted thereto from the other signal generating means; second means for indicating whether the processor is available for executing a supervisory task; third means responsive to the second means for applying a transfer signal to the coupling means for transmission to the other processor; and fourth means responsive to the first, second, and third means for executing a supervisory task when available therefor and either an attention needed signal assigned initial primary priority is received or an attention needed signal assigned initial secondary priority and a transfer signal are received simultaneously.

Claim 30

Dependent Claim 280 words

A data processing system comprising: first and second sources supplying attention needed signals, each attention needed signal indicating the existence of an external interrupt task which must be handled; a plurAlity of processors; each processor including means for handling the processing of interrupt tasks, means for generating a control signal indicating whether its interrupt handling means is currently available or unavailable for processing an interrupt task, means responsive to the control signal for selectively enabling its interrupt handling means to respond to or not enabling it to respond to request signals to process an interrupt task, and means for generating a transfer signal when its interrupt handling means is unavailable; means for coupling the processors together to form a first loop and a second loop for carrying transfer signals for dynamically distributing the task of handling an interrupt task in a first direction and a second direction respectively; means for assigning to a first one of the processors highest priority with respect to the first source, and for assigning a second, different one of the processors highest priority with respect to the second source; said first and second assigned processors further including means for providing an interrupt request signal to their respective interrupt handling means in response to each attention needed signal supplied by the first and second sources respectively, and each processor further including first and second gating means enabled by the coincidence of a transfer signal coupled thereto by the first loop and the second loop respectively and an attention needed signal supplied by a source with respect to which it has not been assigned highest priority for providing interrupt request signals to their corresponding interrupt handling means.

Claim 31

Dependent Claim 280 words

A data processing system comprising: first and second sources supplying attention needed signals, each attention needed signal indicating the existence of an external interrupt task which must be handled; a plurAlity of processors; each processor including means for handling the processing of interrupt tasks, means for generating a control signal indicating whether its interrupt handling means is currently available or unavailable for processing an interrupt task, means responsive to the control signal for selectively enabling its interrupt handling means to respond to or not enabling it to respond to request signals to process an interrupt task, and means for generating a transfer signal when its interrupt handling means is unavailable; means for coupling the processors together to form a first loop and a second loop for carrying transfer signals for dynamically distributing the task of handling an interrupt task in a first direction and a second direction respectively; means for assigning to a first one of the processors highest priority with respect to the first source, and for assigning a second, different one of the processors highest priority with respect to the second source; said first and second assigned processors further including means for providing an interrupt request signal to their respective interrupt handling means in response to each attention needed signal supplied by the first and second sources respectively, and each processor further including first and second gating means enabled by the coincidence of a transfer signal coupled thereto by the first loop and the second loop respectively and an attention needed signal supplied by a source with respect to which it has not been assigned highest priority for providing interrupt request signals to their corresponding interrupt handling means.

Claim 32

Dependent Claim 29 words

A programmable data processing system comprising: a. a plurality of input and/or output units providing attention needed signals; b. a plurality of digital data processors; c. for each processor

Claim 33

Dependent Claim 29 words

A programmable data processing system comprising: a. a plurality of input and/or output units providing attention needed signals; b. a plurality of digital data processors; c. for each processor

Claim 34

Dependent Claim 53 words

A system according to claim 10 wherein the transfer circuits comprise at least first and second transfer circuits; means for coupling the first transfer circuits together for transfer of interrupt requests in one direction between processors; and means for coupling the second transfer circuits together for transfer in a second direction between processors.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1975-05-23	1975-11-22	1976-05-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1979-05-23	1979-11-22	1980-05-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1983-05-23	1983-11-22	1984-05-23	$7700.00	Window Closed / Lapsed

Multi-processor processing system having interprocessor interrupt apparatus

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