Patent US3317855A successfully refreshed from Google Patents.
Patent US3665398A successfully refreshed from Google Patents.
US3665398A
Expired / Lapsed
US
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Input/output multiplex control system
Assignee: KOGYO GYUSTIUM
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Filing: 1969-04-02
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Granted: 1972-05-23
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Expires: 1989-04-02
Abstract
Abstract An input and output control system is disclosed including at least one channel and input-output devices which are connected by a set of interconnecting lines which include a data input bus adapted to transfer data from said input-output devices to said channel and a data output bus adapted to transfer data from said channel to said input-output devices. An improved system of a bus type connection system is defined in which connection of one channel and a plurality of input-output devices is attained by said set of interconnecting lines and said input-output devices is attained by said set of interconnecting lines and said inputoutput devices utilize one interconnecting line in timedivisional manner, said improved system being adapted to select one from among said several input-output devices said one having a request to be coupled with the channel. According to the improved system, it is therefore possible that the several inputoutput devices to be connected to the channel can impart the connecting requirement to the channel unit by utilizing the data input bus without providing signaling lines provided inherently on each of said devices, and that designation of any input-output device to be coupled can be attained by utilizing the data output bus without providing lines for designating connection of a required input-output device on the channel.
Inventors
- 👤 Hidetoshi Kawai
- 👤 Hajime Iizuka
- 👤 Takuo Shinkai
- 👤 Yoshiro Yoshioka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:09
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
295 words
An apparatus for controlling input-output devices for an electronic computer system including at least one channel unit and a plurality of input-output devices, which apparatus comprises: a set of interconnecting lines for connecting said channel unit with said input-output devices so as to form a bus system, said interconnecting lines including a data input bus connected to transfer data from one of said input-output devices to said channel unit; a data output bus connected to transfer data from said channel unit to said one of said input-output devices; and sequence control lines for controlling information transmission through the input-output buses, said channel unit comprising a first selection signal sending circuit to instruct each input-output device to send a request to the input bus in order to select one input-output device requiring to be connected with the channel unit from among the several input-output devices; a priority determining circuit to read out said request transmitted through the input bus thereby to determine the highest priority input-output device; a circuit for sending out the output of said priority determining circuit into the output bus, a second selecTion signal sending circuit for instructing each input-output device to read out the signal passing through said output bus; and wherein each of said input-output devices comprises a circuit for sending out a signal to a predetermined data line of the input bus in response to the first selection signal from the channel unit and a circuit adapted to read out the output bus line to determine whether said input-output device is selected or not, whereby said one set of interconnecting lines are time-divisionally and commonly used for the input-output devices and for only a time period when data transfer is carried out between one input-output device and the channel unit.
Claim 2
Independent Claim
295 words
An apparatus for controlling input-output devices for an electronic computer system including at least one channel unit and a plurality of input-output devices, which apparatus comprises: a set of interconnecting lines for connecting said channel unit with said input-output devices so as to form a bus system, said interconnecting lines including a data input bus connected to transfer data from one of said input-output devices to said channel unit; a data output bus connected to transfer data from said channel unit to said one of said input-output devices; and sequence control lines for controlling information transmission through the input-output buses, said channel unit comprising a first selection signal sending circuit to instruct each input-output device to send a request to the input bus in order to select one input-output device requiring to be connected with the channel unit from among the several input-output devices; a priority determining circuit to read out said request transmitted through the input bus thereby to determine the highest priority input-output device; a circuit for sending out the output of said priority determining circuit into the output bus, a second selecTion signal sending circuit for instructing each input-output device to read out the signal passing through said output bus; and wherein each of said input-output devices comprises a circuit for sending out a signal to a predetermined data line of the input bus in response to the first selection signal from the channel unit and a circuit adapted to read out the output bus line to determine whether said input-output device is selected or not, whereby said one set of interconnecting lines are time-divisionally and commonly used for the input-output devices and for only a time period when data transfer is carried out between one input-output device and the channel unit.
Claim 3
Independent Claim
319 words
An apparatus for controlling input-output devices for an electronic computer system including at least one channel unit and a plurality of input-output devices, which apparatus comprises: a set of interconnecting lines for connecting said channel unit with said input-output devices so as to form a bus system, said interconnecting lines including a data input bus connected to transfer data from one of said input-output devices to said channel unit; a data output bus connected to transfer data from said channel unit to one of said input-output devices; and sequence control lines for controlling information transmission through the input-output buses, said channel unit comprising a first selection signal sending circuit to instruct each input-output device to send a request to the input bus in order to select one input-output device requiring to be connected with the channel unit from among said input-output devices; a priority determining circuit to read out said request transmitted through the input bus thereby to determine the highest priority input-output device, said priority determining circuits sending out a signal to a data line on the data output bus, said data line corresponding respectively to said plural input-output devices; a second selection signal sending circuit for instructing each input-output device to read out the signal passing through said output bus; and wherein each of said input-output devices comprises a circuit for sending out a signal to a data line of the data input bus in response to the first selection signal from the channel unit said data line being predetermined in corres-pondence with a respective one of said input-output devices and a circuit adapted to read out the output bus line to determine whether said input-output device is selected or not, whereby said one set of interconnecting lines are time-divisionally and commonly used for the input-output devices and for only a time period when data transfer is carried out between one input-output device and the channel unit.
Claim 4
Independent Claim
319 words
An apparatus for controlling input-output devices for an electronic computer system including at least one channel unit and a plurality of input-output devices, which apparatus comprises: a set of interconnecting lines for connecting said channel unit with said input-output devices so as to form a bus system, said interconnecting lines including a data input bus connected to transfer data from one of said input-output devices to said channel unit; a data output bus connected to transfer data from said channel unit to one of said input-output devices; and sequence control lines for controlling information transmission through the input-output buses, said channel unit comprising a first selection signal sending circuit to instruct each input-output device to send a request to the input bus in order to select one input-output device requiring to be connected with the channel unit from among said input-output devices; a priority determining circuit to read out said request transmitted through the input bus thereby to determine the highest priority input-output device, said priority determining circuits sending out a signal to a data line on the data output bus, said data line corresponding respectively to said plural input-output devices; a second selection signal sending circuit for instructing each input-output device to read out the signal passing through said output bus; and wherein each of said input-output devices comprises a circuit for sending out a signal to a data line of the data input bus in response to the first selection signal from the channel unit said data line being predetermined in corres-pondence with a respective one of said input-output devices and a circuit adapted to read out the output bus line to determine whether said input-output device is selected or not, whereby said one set of interconnecting lines are time-divisionally and commonly used for the input-output devices and for only a time period when data transfer is carried out between one input-output device and the channel unit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-23 | 1975-11-22 | 1976-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-23 | 1979-11-22 | 1980-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-23 | 1983-11-22 | 1984-05-23 | $7700.00 | Window Closed / Lapsed |