Method of making or modifying a pn-junction by ion implantation

Claim 2

Method for altering the impurity concentration profile of a region in semiconductor substrate comprising the steps of heating said substrate to a temperature of about 100* to 600* C., ion implanting impurity ions into the region to be altered and stepping the bombardment energy to obtain the desired impurity profile.

Claim 3

Method for forming an integrated circuit having immediately adjaceNt NPN- and PNP-transistors comprising the steps of ion implanting in a P-type substrate a first region of N-type impurity to form the collector of said NPN-transistor, ion implantaing within said first region a second region of P-type impurity to form the base region of said NPN-transistor, ion implanting within said second region a third region of N-type impurity to form the emitter region of said NPN-transistor, ion implanting within said substrate and immediately adjacent said first region, a fourth region of N-type impurity to form the base region of said PNP-transistor, said substrate being the collector region of said PNP-transistor, ion implanting within said fourth region a fifth region of P-type impurity to form the emitter region of said PNP-transistors, and stepping the bombardment energy in the ion implanting of selected regions.

Claim 4

The method of claim 4 with the additional step of ion implanting a lifetime killer impurity into the collector regions near the base-collector junctions of said transistors.

Claim 5

Method for forming an integrated circuit having a PNP-transistor and NPN-transistor in close proximity, comprising the steps of ion implanting in an N-type substrate a first region of P-type impurity to form the collector of said PNP-transitor, ion implanting with said first region a second region of N-type impurity to form the base region of said PNP-transistor, ion implanting within said second region a third region of P-type impurity to form the emitter region of said PNP-transisotr, ion implanting within said substrate and immediately adjacent said first region a fourth region of P-type impurity to form the base region of said NPN-transistor, said substrate being the collector region of said NPN-transistor, ion implanting within said fourth region a fifth region of N-type impurity to form the emitter region of said NPN-transistor, and stepping the bombardment energy during ion implanting of each region, thereby obtaining essentially constant impurity concentration junctions.

Claim 6

The method of claim 6 with the additional step of ion implanting a lifetime killer impurity into the collector regions near the base-collector junctions of said transistors.

Claim 7

Method for forming an integrated circuit having two immediately adjacent transistors of different electrical characteristics within a semiconductor substrate containing an impurity concentration of the first type, comprising the steps of ion implanting a first region of the second impurity type at a first impurity concentration and depth to form the collector region of a first transistor, ion implanting a second region of the second impurity type at a second impurity concentration and depth to form the collector region of a second transistor, said first and second regions being immediately adjacent, ion implanting within said first region a third region of the first impurity type at a third impurity concentration and depth to form the base region of said first transistor, ion implanting within said second region a fourth region of the first impurity type at a fourth impurity concentration and depth to form the base region of said second transistor, ion implanting within said third region a fifth region of the second impurity type at a fifth impurity concentration and depth to form the emitter region of said first transistor, ion implanting within said fourth region a sixth region of the second impurity type at a sixth impurity concentration and depth to form the emitter region of said second transistor, and stepping the ion bombardment energy in the ion implanting of each said region to obtain essentially constant impurity concentration junctions.

Claim 8

Method for making a transistor having a sub-collector junction, a base-collector junction, and a base-emitter junction, in a monocrystalline semiconductor substrate having a concentration of impUrity of the first type, comprising the steps of ion implanting in said substrate a sub-collector region and a collector region of an impurity of the second type, said sub-collector region having a high impurity concentration, and said collector region having a low impurity concentration and extending between said sub-collector region and the surface of said substrate, ion implanting within said collector region a base region of an impurity of the first type, ion implanting within said base region an emitter region of an impurity of the second type, and stepping the ion bombardment energy during each ion implanting step obtaining essentially constant impurity concentration junctions.

Claim 9

Method for forming a transistor in a substrate containing an impurity of the second type, comprising the steps of heating said substrate to a temperature from 100* to 600* C., and holding said substrate at said temperature through the following ion implantation steps, implanting a shallow region of an impurity of the first type in said substrate, said substrate being the collector region of said transistor, ion implanting a second region of said impurity of the first type through and to a greater depth than said shallow region, ion implanting into said second region an impurity of the second type which diffuses slower than said impurity of the first type, heating said substrate for a time and to a temperature sufficient to diffuse said impurity of the first type out of said second region to form a narrow base region surrounding said second region, said second region thereby becoming the emitter region of said transistor.

Claim 10

The method of claim 10 where the implanting of the impurities into the first and second regions is performed at varying bombardment energies to obtain essentially constant impurity concentration throughout each ion implanted region.

Claim 11

The method of claim 10 with the additional step of ion implanting a lifetime killer impurity into the collector region near to the base-collector junction of said transistor.

Claim 12

The method of claim 10 with the additional step of altering the impurity concentration of a region by ion implanting impurity ions into the region to be altered.

Claim 13

Method for forming a high speed transistor in a substrate containing a concentration of impurity of the first type, comprising the steps of ion implanting in said substrate a sub-collector region and a collector region containing an impurity of the second type, said sub-collector region having a high impurity concentration, and said collector region having a low impurity concentration and extending between said sub-collector region and the surface of said substrate, implanting within said collector region a shallow region of an impurity of the first type, ion implanting a fourth region through said shallow region to a greater depth the impurity of the first type, ion implanting into said fourth region an impurity of the second type which diffuses slower than said impurity of the first type, heating said substrate for a time and to a temperature sufficient to diffuse said impurity of the first type out of the fourth region to form a narrow base region surrounding said fourth region, said fourth region thereby becoming the emitter region of said transistor.

Claim 14

The method of claim 14 where each ion implanting step is performed at varying bombardment energies to obtain an essentially constant impurity concentration throughout each ion implanted region.

Claim 15

The method of claim 14 with the additional step of ion implanting lifetime killer impurities into the collector region near the junction between said collector and base regions after the step of heating the substrate to form said base region.

Claim 16

The method of claim 14 with the additional step of altering the impurity concentration in a region by ion implanting impurity ions into said region to be altered.

Claim 17

Method for making a plurality of high speed transistors having sub-collector junctions in a substrate containing an impurity concentration of the first type, comprising the steps of heating said substrate to a temperature from 100* to 600* C., ion implanting in said substrate a first sub-collector region and a first collector region of an impurity of the second type, said first sub-collector region having a high impurity concentration, and said first collector region having a low impurity concentration and extending between said first sub-collector region and the surface of said substrate, ion implanting in said substrate a second sub-collector region and a second collector region of an impurity of the second type, said second sub-collector region having a high impurity concentration, and said second collector region having a low impurity concentration and extending between said second sub-collector region and the surface of said substrate, implanting a third shallow region of an impurity of the first type within said first collector region, implanting a shallow fourth region of an impurity of the first type within said second collector region, ion implanting in a fifth region within said first collector region and through and to a greater depth than said third region the impurity of the first type, ion implanting in a sixth region with said second collector region and to a greater depth than said fourth region the impurity of the first type, ion implanting into said fifth region an impurity of the second type which diffuses slower than said impurity of the first type, ion implanting into said sixth region an impurity of the second type which diffuses slower than said impurity of the first type, heating said substrate for a time and to a temperature sufficient to diffuse said impurities of the first type out of said fifth and sixth regions, thereby forming a first base region surrounding said fifth region and a second base region surrounding said sixth region, said fifth region becoming the first emitter region and said sixth region becoming the second emitter region, and cooling said substrate to a temperature between 100* to 600* C.

Claim 18

The method of claim 18 with the additional step of, prior to the implantation of said isolation region, masking the surface of said substrate to prevent the implantation of impurities into regions other than said isolation region.

Claim 19

The method of claim 18 where each ion implanting step is performed at varying bombardment energies to obtain essentially constant impurity concentration throughout each ion implanted region.

Claim 20

The process of claim 18 with the additional steps of ion implanting a lifetime killer impurity into the first collector region adjacent the junction between said first collector and first base regions, and ion implanting a lifetime killer impurity into said second collector region adjacent the junction between said second collector and second base regions, said ion implanting of lifetime killer impurities being performed after the process steps of heating the substrate to form the first and second base regions and cooling the substrate to 100* to 600* C.

Claim 21

The method of claim 18 with the additional step of altering the impurity concentration of a region by ion implanting impurity ions into said region to be altered.

Claim 22

The method of claim 18 with the additional step of ion implanting a connective channel region with an impurity of the type implanted in the regions to be connected between two regions containing an impurity concentration of the same type.

Claim 23

Method for forming a plurality of transistors having sub-collector junctions, comprising the steps of implanting into a substrate containing a concentration of impurity of the first type a first sub-collector region and a second sub-collector region of impurity of the second type, epitaxially growing over said substrate and said first and second sub-collector regions a collector region containing an impurity of the second type, implanting in said collector region and over said first sub-collector region a shallow third region of impurity of the first type, implanting in said collector region and over said second sub-collector region a shallow fourth region containing an impurity of the first type, ion implanting in a fifth region within said collector region and through and to a greater depth than said third region an impurity of the first type, ion implanting into said fifth region an impurity of the second type which diffuses slower than said impurity of the first type previously implanted into said fifth region, ion implanting in a sixth region within said collector region and through and to a greater depth than said fourth region an impurity of the first type, ion implanting into said sixth region an impurity of the second type which diffuses slower than the impurity of the first type previously implanted into said sixth region, heating said substrate for a time and to a temperature sufficient to diffuse the impurity of the first type out of said fifth region to form a first base region surrounding said fifth region, and to diffuse the impurity of the first type out of said sixth region to form a second base region surrounding said sixth region, ion implanting in an isolation region through said collector region and into said substrate between said first and second sub-collector regions an impurity of the first type.

Claim 24

The method of claim 24 where each ion implanting step is performed at varying bombardment energies to obtain essentially constant impurity concentration throughout each ion implanted region.

Claim 25

Method for forming a conductive channel having a predetermined electrical resistance in a substrate material containing an impurity of the first type, comprising the steps of implanting a first and second low resistant contact region of an impurity of the second type, ion implanting a high resistant conductive channel of the first type impurity interconnecting said first and second contact regions; monitoring the resistance between said first and second contact regions, and trimming the resistance value of said conductive channel by implanting ions of the second impurity type into said channel, terminating the implantation of said second type impurity when the resistance between said first and second contact regions drops to a predetermined lower value.

Claim 28

Method for altering the junction depth in a substrate between a first region containing an impurity concentration of the first type and a second region containing an impurity concentration of the second type, comprising the steps of ion implanting into said second region at the junction between said first and second regions an impurity of the first type.

Claim 29

Method for altering the juNction depth in a substrate of the junction between a first region containing an impurity of the first type and a second region containing an impurity of the second type, comprising the steps of ion implanting into said first region at the junction between said first and second regions an impurity of the second type.

Claim 30

Method for reducing the minority carrier lifetime in a collector region of a semiconductor device comprising the steps of ion implanting into said region lifetime killer impurity ions within an area of about 1 micron from the collector-base junction.