Patent US3648252A successfully refreshed from Google Patents.
US3648252A
Expired / Lapsed
US
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Multiprogrammable, multiprocessor computer system
Assignee: Honeywell Inc
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Filing: 1969-11-03
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Granted: 1972-03-07
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Expires: 1989-11-03
Abstract
Abstract A multiprogrammable, multiprocessor computer system is disclosed including at least one central processor for performing arithmetic and logic operations, at least one input/output processor for performing input and output operations, storage means connected with each of the processors and adapted for storing central processor programs associated with the central processor and channel programs associated with the input/output processor, and a multiprocess controller connected to each of the processors for accepting control of a program from a processor in response to an interrupt and providing control of another program to that particular processor in accordance with a predetermined priority arrangement including a plurality of activity state indicators, one associated with each of the programs in the storage means, each of the activity state indicators representing the activity state of its respective program.
Inventors
- 👤 John E Thron
- 👤 William E Woods
- 👤 Ronald Bellettiere
- 👤 Howard Stein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 23:41
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26; G06F15/00; G06F15/16
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
478 words
A multiprogrammable, multiprocessor computer system comprising: A. a first processor; B. a second processor; C. a main memory coupled with both a first group of programs to be executed in said first processor and a second group of programs to be executed in said second processor, said first processor presently executing one of said programs in said first group and said second processor presently executing one of said programs in said second group; D. means for generating a first interrupt; E. means for generating a second interrupt; F. multiprocess control means coupled with both said first processor and said second processor, said control means comprising: 1. a first plurality of activity state indicators, one indicator of said first plurality for each program of said first group, 2. means for setting said state indicators of said first plurality in a first predetermined priority arrangement so as to indicate an active or inactive condition of the corresponding programs of said first group, 3. a second plurality of activity state indicators, one indicator of said second plurality for each program of said second group, 4. means for setting said state indicators of said second plurality in a second predetermined priority arrangement so as to indicate in active or inactive condition of the corresponding programs of said second group, 5. means responsive to said first interrupt for modifying the activity state of said indicator of said first plurality corresponding to said program being currently executed in said first processor, 6. means responsive to said second interrupt for modifying the activity state of said indicator of said second plurality corresponding to said program being currently executed in said second processor, 7. first means, coupled to said first plurality of indicators and coupled for response after the modifying of said indicators by said means responsive to said first interrupt, for determining the identity of the next program having an active condition and having the highest priority of said programs in said first group, 8. second means, coupled to said second plurality of indicators and coupled for response after the modifying of said indicators by said means responsive to said second interrupt, for determining the identity of a program having an active condition and having the highest priority of said programs in said second group, 9. means for providing said first processor with the identity of the program identified by said first means for determining, and 10. means for providing said second processor with identity of the program identified by said second means for determining; G. means included in said first processor for interchanging for execution in said processor the program being presently executed with the program identified by said first means for determining; and H. means included in said second processor for interchanging for execution in said second processor the program being presently executed with the program identified by said second means for determining.
Claim 2
Dependent Claim
478 words
A multiprogrammable, multiprocessor computer system comprising: A. a first processor; B. a second processor; C. a main memory coupled with both a first group of programs to be executed in said first processor and a second group of programs to be executed in said second processor, said first processor presently executing one of said programs in said first group and said second processor presently executing one of said programs in said second group; D. means for generating a first interrupt; E. means for generating a second interrupt; F. multiprocess control means coupled with both said first processor and said second processor, said control means comprising: 1. a first plurality of activity state indicators, one indicator of said first plurality for each program of said first group, 2. means for setting said state indicators of said first plurality in a first predetermined priority arrangement so as to indicate an active or inactive condition of the corresponding programs of said first group, 3. a second plurality of activity state indicators, one indicator of said second plurality for each program of said second group, 4. means for setting said state indicators of said second plurality in a second predetermined priority arrangement so as to indicate in active or inactive condition of the corresponding programs of said second group, 5. means responsive to said first interrupt for modifying the activity state of said indicator of said first plurality corresponding to said program being currently executed in said first processor, 6. means responsive to said second interrupt for modifying the activity state of said indicator of said second plurality corresponding to said program being currently executed in said second processor, 7. first means, coupled to said first plurality of indicators and coupled for response after the modifying of said indicators by said means responsive to said first interrupt, for determining the identity of the next program having an active condition and having the highest priority of said programs in said first group, 8. second means, coupled to said second plurality of indicators and coupled for response after the modifying of said indicators by said means responsive to said second interrupt, for determining the identity of a program having an active condition and having the highest priority of said programs in said second group, 9. means for providing said first processor with the identity of the program identified by said first means for determining, and 10. means for providing said second processor with identity of the program identified by said second means for determining; G. means included in said first processor for interchanging for execution in said processor the program being presently executed with the program identified by said first means for determining; and H. means included in said second processor for interchanging for execution in said second processor the program being presently executed with the program identified by said second means for determining.
Claim 3
Dependent Claim
33 words
means for setting said state indicators of said first plurality in a first predetermined priority arrangement so as to indicate an active or inactive condition of the corresponding programs of said first group,
Claim 4
Dependent Claim
33 words
means for setting said state indicators of said first plurality in a first predetermined priority arrangement so as to indicate an active or inactive condition of the corresponding programs of said first group,
Claim 5
Dependent Claim
90 words
A system as defined in claim 1 further comprising: A. means in said first processor for comparing the priOrity of the program being presently executed therein with the priority of said program identified by said first means for determining; and B. means coupled with said means for comparing for allowing said program being presently executed in said first processor to continue being executed if the priority of the program being presently executed in said processor is greater than the priority of said program identified by said first means for determining.
Claim 6
Dependent Claim
62 words
A system as defined in claim 2 further comprising means for suspending the execution of the program being presently executed in said processor and executing the program identified by said first means for determining if the priority of the program being presently executed in said first processor is less than the priority of said program identified by said first means for determining.
Claim 7
Dependent Claim
20 words
a second plurality of activity state indicators, one indicator of said second plurality for each program of said second group,
Claim 8
Dependent Claim
20 words
a second plurality of activity state indicators, one indicator of said second plurality for each program of said second group,
Claim 9
Dependent Claim
33 words
means for setting said state indicators of said second plurality in a second predetermined priority arrangement so as to indicate in active or inactive condition of the corresponding programs of said second group,
Claim 10
Dependent Claim
33 words
means for setting said state indicators of said second plurality in a second predetermined priority arrangement so as to indicate in active or inactive condition of the corresponding programs of said second group,
Claim 11
Dependent Claim
147 words
A system as defined in claim 3 further comprising: A. second means in said second processor for comparing the priority of the program being presently executed therein with the priority of said program identified by said means for determining; B. means coupled with said second means for comparing for allowing said program being presently executed in said second processor to continue being executed if the priority of the program being presently executed in said second processor is greater than the priority of said program identified by said second means for determining; and C. means for suspending the execution of the program being presently executed in said second processor and executing the program identified by said second means for determining if the priority of the program being presently executed in said second processor is less than the priority of said program identified by said second means for determining.
Claim 12
Dependent Claim
149 words
A system as defined in claim 1 wherein said first processor is a central processor and wherein said second processor is an input/output processor, said system further comprising: A. a plurality of device controllers coupled with said input/output processor, each of said plurality of device controllers including a first priority means; and wherein said multiprocessor control means further comprises: B. a second priority means interconnected by a priority bus to each of said first priority means, C. means responsive to said second means for determining and said input/output processor for submitting a service request to said input/output processor; D. means responsive to said second priority means for indicating the availability of service from said input/output processor to said control means; and E. means responsive to a request acknowledge from said input/output processor and responsive to said means for indicating, for delivering an execute command directive to said input/output processor.
Claim 13
Dependent Claim
29 words
means responsive to said first interrupt for modifying the activity state of said indicator of said first plurality corresponding to said program being currently executed in said first processor,
Claim 14
Dependent Claim
29 words
means responsive to said first interrupt for modifying the activity state of said indicator of said first plurality corresponding to said program being currently executed in said first processor,
Claim 15
Dependent Claim
29 words
means responsive to said second interrupt for modifying the activity state of said indicator of said second plurality corresponding to said program being currently executed in said second processor,
Claim 16
Dependent Claim
29 words
means responsive to said second interrupt for modifying the activity state of said indicator of said second plurality corresponding to said program being currently executed in said second processor,
Claim 17
Dependent Claim
191 words
A system as defined in claim 5 wherein: A. said main memory is adapted to store a channel status word for each of said second group of programs representative of the status of each of said second group of programs, each of said channel status words including first and second parts; and wherein said input/output processor further comprises: B. a channel register for holding said first or second part of one of said channel status words; C. means for transferring into said main memory said first part of said one of said channel status words presently in said channel register; D. means for transferring into said channel register said first part of a new one of said channel status words in response to identification of said new one of said channel status words by said second means for determining; E. wherein said first part of said channel status word includes an address of an order transmit command; and F. means for transferring to a second register an order transmit command corresponding to the address in said first part of said new one of said channel status words in said channel register.
Claim 18
Dependent Claim
40 words
The system of claim 6 in which said input/output processor includes means for addressing one of said device controllers and includes means for sending said order transmit command in said second register to said one of said device controllers addressed.
Claim 19
Dependent Claim
51 words
first means, coupled to said first plurality of indicators and coupled for response after the modifying of said indicators by said means responsive to said first interrupt, for determining the identity of the next program having an active condition and having the highest priority of said programs in said first group,
Claim 20
Dependent Claim
51 words
first means, coupled to said first plurality of indicators and coupled for response after the modifying of said indicators by said means responsive to said first interrupt, for determining the identity of the next program having an active condition and having the highest priority of said programs in said first group,
Claim 21
Dependent Claim
50 words
second means, coupled to said second plurality of indicators and coupled for response after the modifying of said indicators by said means responsive to said second interrupt, for determining the identity of a program having an active condition and having the highest priority of said programs in said second group,
Claim 22
Dependent Claim
50 words
second means, coupled to said second plurality of indicators and coupled for response after the modifying of said indicators by said means responsive to said second interrupt, for determining the identity of a program having an active condition and having the highest priority of said programs in said second group,
Claim 23
Dependent Claim
168 words
A system as defined in claim 7 in which said input/output processor further comprises: A. means responsive to a request from a said device controller or said multiprocess control means, for initiating an inhibit to all said device controllers and said multiprocess control means to prevent further requests from said multiprocess control means and said device controllers; B. means, pursuant to said inhibit, for initiating an acknowledge to the addressed said device controller; C. means, responsive to an accept from said addressed device controller to transfer said first part of said channel status word from said first register to said main memory and replace it with said second part; and D. means, responsive to a wait from said addressed device controller, to transfer said first part of said channel status word from said first register to said main memory and replace it with a said first part of a said channel status word of another of said second group of programs identified by said second means for determining.
Claim 24
Dependent Claim
37 words
A system as defined in claim 1 in which said main memory stores a program status word for each of said first group of programs representative of the status of each of said first group of programs.
Claim 25
Dependent Claim
20 words
means for providing said first processor with the identity of the program identified by said first means for determining, and
Claim 26
Dependent Claim
20 words
means for providing said first processor with the identity of the program identified by said first means for determining, and
Claim 27
Dependent Claim
78 words
means for providing said second processor with identity of the program identified by said second means for determining; G. means included in said first processor for interchanging for execution in said processor the program being presently executed with the program identified by said first means for determining; and H. means included in said second processor for interchanging for execution in said second processor the program being presently executed with the program identified by said second means for determining.
Claim 28
Dependent Claim
78 words
means for providing said second processor with identity of the program identified by said second means for determining; G. means included in said first processor for interchanging for execution in said processor the program being presently executed with the program identified by said first means for determining; and H. means included in said second processor for interchanging for execution in said second processor the program being presently executed with the program identified by said second means for determining.
Claim 29
Dependent Claim
133 words
A system as defined in claim 9 in which said first processor further comprises: A. a first register for holding a program status word; B. a second register for holding the identification code of the program of said first group being presently executed by said first processor; C. means for comparing the code in said second register with the code of the program identified by said first means for determining; and D. means responsive to said means for comparing for returning the program status word from said first register to said main memory and replacing it with the program status word of the program identified by said first means for determining, and for replacing the code in said second register with the code of the program identified by said first means for determining.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-07 | 1975-09-06 | 1976-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-07 | 1979-09-06 | 1980-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-07 | 1983-09-06 | 1984-03-07 | $7700.00 | Window Closed / Lapsed |