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US3636443A
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Method of testing devices using untested devices as a reference standard
Assignee: International Business Machines Corp
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Filing: 1970-10-29
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Granted: 1972-01-18
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Expires: 1990-10-29
Abstract
Abstract A method of testing circuit chips using untested chips as a standard. A portion of the untested chips is selected at random and used as a reference standard. A random pulse generator generates patterns of pulses which are applied to the test standard chips and also successively to each of the remaining chips. A majority logic gate is employed to determine the majority outputs of the test standard chips. Each majority output is compared with the respective outputs of the remaining chips to determine which of the latter are qualified. Some of the qualified chips are then substituted for the test standard chips and the cycle is then repeated with the qualified chips, and repeated again with the twice-qualified chips. With each successive cycle the probability of qualifying good chips converges toward unity.
Inventors
- 👤 Shanker Singh
- 👤 Vijendrap P Singh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:55
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
105 words
A method of testing a number of components and comprising the steps of selecting from said number a set of components to be used as a test standard, applying a pattern of pulses to said test standard and successively to each of the remaining components of said number, determining the output signals represenTative of the majority of the responses of said test standard, comparing the majority responses of the test standard components with the responses of the remaining components, identifying as qualified those remaining components having responses matching the majority responses, and repeating said selecting, applying, determining, comparing and identifying steps with said qualified components.
Claim 2
Independent Claim
105 words
A method of testing a number of components and comprising the steps of selecting from said number a set of components to be used as a test standard, applying a pattern of pulses to said test standard and successively to each of the remaining components of said number, determining the output signals represenTative of the majority of the responses of said test standard, comparing the majority responses of the test standard components with the responses of the remaining components, identifying as qualified those remaining components having responses matching the majority responses, and repeating said selecting, applying, determining, comparing and identifying steps with said qualified components.
Claim 3
Dependent Claim
17 words
A method of testing components as recited in claim 1 wherein said pattern of pulses is random.
Claim 4
Dependent Claim
36 words
A method of testing components as recited in claim 1 and comprising a plurality of repeated iterations of said selecting, applying, determining, comparing and identifying steps, each iteration utilizing the chips qualified in the preceding iteration.
Claim 5
Dependent Claim
171 words
A method as recited in claim 1 and having a plurality of iterations each including said selecting, applying, determining, comparing and identifying steps applied to the respective qualified components of each prior iteration, said pattern of pulses being randomly generated. 5. A method of testing a number of circuit chips and comparing the steps of dividing the number of circuit chips into a plurality of sets, selecting from each set a subset of circuit chips to be used as a test standard, applying patterns of pulses to said test standard circuit chips and also successively to each of the remaining circuit chips of each respective set, determining the output signals representative of the majority of the responses of said test standard circuit chips, comparing the remaining circuit chip responses with said majority responses, identifying as qualified those remaining circuit chips having responses matching said majority responses, collecting those qualified circuit chips having responses matching said respective majority responses, and repeating all of the above steps with the remaining qualified circuit chips.
Claim 6
Dependent Claim
17 words
A method of testing components as recited in claim 5 wherein said patterns of pulses are random.
Claim 7
Dependent Claim
33 words
A method as recited in claim 6 having a plurality of iterations each including said dividing, selecting, applying, determining, comparing and identifying steps applied to the respective qualified circuits of each prior iteration.
Claim 8
Independent Claim
140 words
A method of testing circuits using untested circuits as a reference standard, said method comprising the steps of dividing the untested circuits into a plurality of sets, selecting for each set a subset of circuits for use as a reference standard, applying a sequence of signals to each circuit of each subset, determining the response to said signal of the majority of said circuits of each subset, applying said sequence of signals to each of the other circuits of each set, comparing each of said majority responses respectively to each response of said other circuits of each set, classifying as qualified those circuits of the set which have the same response as the majority response of the respective reference standard circuits, and repeating said dividing, selecting, applying, determining, comparing and classifying steps utilizing only said qualified circuits of each set.
Claim 9
Independent Claim
140 words
A method of testing circuits using untested circuits as a reference standard, said method comprising the steps of dividing the untested circuits into a plurality of sets, selecting for each set a subset of circuits for use as a reference standard, applying a sequence of signals to each circuit of each subset, determining the response to said signal of the majority of said circuits of each subset, applying said sequence of signals to each of the other circuits of each set, comparing each of said majority responses respectively to each response of said other circuits of each set, classifying as qualified those circuits of the set which have the same response as the majority response of the respective reference standard circuits, and repeating said dividing, selecting, applying, determining, comparing and classifying steps utilizing only said qualified circuits of each set.
Claim 10
Dependent Claim
17 words
A method of testing components as recited in claim 8 wherein said patterns of pulses are random.
Claim 11
Dependent Claim
32 words
A method as recited in claim 9 having a plurality of iterations each including said dividing, selecting, applying determining, comparing and classifying applied to the respective qualified circuits of each prior iteration.
Claim 12
Independent Claim
93 words
A method of testing a set of components and comprising the steps of selecting from said set a subset of components to be used as a test standard, applying a pattern of pulses to said test standard and successively to each of the remaining components of said set, determining the output signals representative of the majority of the responses of said test standard, comparing the majority of responses of the test standard components with the responses of the remaIning components, and identifying as qualified those remaining components having responses matching the majority responses.
Claim 13
Independent Claim
93 words
A method of testing a set of components and comprising the steps of selecting from said set a subset of components to be used as a test standard, applying a pattern of pulses to said test standard and successively to each of the remaining components of said set, determining the output signals representative of the majority of the responses of said test standard, comparing the majority of responses of the test standard components with the responses of the remaIning components, and identifying as qualified those remaining components having responses matching the majority responses.
Claim 14
Dependent Claim
17 words
A method of testing components as recited in claim 11 wherein said patterns of pulses are random.
Claim 15
Dependent Claim
32 words
A method as recited in claim 12 having a plurality of iterations each including said selecting, applying, determining, comparing and identifying steps applied to the respective qualified circuits of each prior iteration.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-17 | 1975-07-19 | 1976-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-17 | 1979-07-19 | 1980-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-17 | 1983-07-19 | 1984-01-18 | $7700.00 | Window Closed / Lapsed |