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US3634665A
Expired / Lapsed
US
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System use of self-testing checking circuits
Assignee: International Business Machines Corp
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Filing: 1969-06-30
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Granted: 1972-01-11
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Expires: 1989-06-30
Abstract
Abstract A self-testing error-checking system for inclusion in a computer comprising a plurality of self-testing check circuits, each said circuit having a two-rail complementary output whenever both the circuits being tested and the checking circuit is operating properly and an identical output on each of the two output lines whenever a fault is detected. The improvement which comprises reduction checking means connected to all said two-rail outputs from said checking circuits, and means connected to the output of said reduction checker means for at least indicating that a failure has occurred. The output of said reduction checker itself is two rail and complementary when all inputs are correct and the checker itself is operating properly. The output of the present checking system may be connected to a computer interrupt circuit or to a visual logout means. Alternatively, the system output may be utilized to effect automatic self-repair.
Inventors
- 👤 William C Carter
- 👤 Peter R Schneider
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:56
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/31835; G01R31/3187; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1032
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
190 words
A self-testing error-checking system for inclusion in a computer including a plurality of individual two output signal pair error-checking circuits connected to various portions of the computer, each error-checking circuit having its output signal pair in a code state when the inputs are all correct and the checking circuit itself is functioning properly said system comprising, at least one two-output reduction circuit means for receiving the outputs from a plurality of said two-output checkers, said reduction circuit producing an output signal pair in the code state when all inputs are correct and said circuit is itself functioning properly and a single failure tolerant means for producinG a system failure indication whenever the output signal pair from said reduction circuit is in an error state and wherein the error and code states are selectively chosen from a first identical code pattern and a second complementary code pattern wherein when the error state is represented by the second code pattern the code state is represented by the first code pattern and when the error state is represented by the first code pattern the code state is represented by the first code pattern.
Claim 2
Dependent Claim
190 words
A self-testing error-checking system for inclusion in a computer including a plurality of individual two output signal pair error-checking circuits connected to various portions of the computer, each error-checking circuit having its output signal pair in a code state when the inputs are all correct and the checking circuit itself is functioning properly said system comprising, at least one two-output reduction circuit means for receiving the outputs from a plurality of said two-output checkers, said reduction circuit producing an output signal pair in the code state when all inputs are correct and said circuit is itself functioning properly and a single failure tolerant means for producinG a system failure indication whenever the output signal pair from said reduction circuit is in an error state and wherein the error and code states are selectively chosen from a first identical code pattern and a second complementary code pattern wherein when the error state is represented by the second code pattern the code state is represented by the first code pattern and when the error state is represented by the first code pattern the code state is represented by the first code pattern.
Claim 3
Dependent Claim
55 words
A self-testing error-checking system as set forth in claim 1 wherein said means for producing a system failure indication includes a plurality of logout status light means connected to each output of said reduction circuit means whereby a failure of any single indicating light therein will be visible if an incorrect output is caused thereby.
Claim 4
Dependent Claim
80 words
A self-testing error-checking system as set forth in claim 1 wherein said means for producing a system failure indication comprises a fail-safe stopping switch means connected to the output signal pair of said reduction circuit means for interrupting further operation of said computer until an error is corrected, said switch means being constructed so that a single failure of any logic block therein will either not affect the operation of the switch or cause a stoppage of said computer system.
Claim 5
Dependent Claim
108 words
A self-testing error-checking system as set forth in claim 1 wherein said checking circuits are arranged in rows and columns wherein each row of checking circuits is connected to a first set of primary reduction circuits and wherein each column of said checking circuits is connected to a second set of said primary reduction circuit means, each said primary reduction circuit means having a failure indication means connected to the output thereof whereby an error output from any of said checkers will produce an error indication in both the output indication means connected to said first set and the said second set of said primary reduction circuit means.
Claim 6
Dependent Claim
70 words
A self-testing error-checking system as set forth in claim 4 wherein each of said two sets of primary reduction circuit means is connected to a separate secondary reduction circuit means, the outputs of said secondary reduction circuit means being operative to actuate failure indication means and to interrupt system operation when an error is detected either in one of their inputs or in the secondary reduction circuit means per se.
Claim 7
Dependent Claim
78 words
A self-testing error-checking system as set forth in claim 1 wherein said computing system comprises at least one set of redundant modules connected to at least one utilization means, each module having such a checking system included therein, means for applying the two-rail output from the checking system for each said module to a reconfiguration control circuit means, said reconfiguration means including means for excluding a malfunctioning module and substituting a properly functioning module therefor in the system.
Claim 8
Dependent Claim
102 words
A self-testing error-checking system for use with a redundant computer configuration as set forth in claim 6 wherein said reconfiguration control circuit means includes status register means having a settable state for each available module, means for setting a given state of said status register in accordance with the output of said error-checking system included with each module wherein said status register means utilizes circuitry for a single error correction encoding of the state and the output of said status register includes local decoding logic whereby any single failures in said status register means will not affect the operation of the system.
Claim 9
Dependent Claim
33 words
A self-testing error-checking system as set forth in claim 7 wherein the locally decoded output of the encoded status register is utilized to, in effect, turn the power off in a malfunctioning module.
Claim 10
Dependent Claim
50 words
A self-testing error-checking system as set forth in claim 7 wherein the locally decoded output of said encoded status register switches the output from a just-failed mOdule to the output of another standby module upon detection of an error and means for automatically affecting retry of a previously failed module.
References Cited (Backward Citations)
US3229251A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-10 | 1975-07-12 | 1976-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-10 | 1979-07-12 | 1980-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-10 | 1983-07-12 | 1984-01-11 | $7700.00 | Window Closed / Lapsed |