Patent US3624372A successfully refreshed from Google Patents.
US3624372A
Expired / Lapsed
US
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Checking and fault-indicating arrangements
Assignee: Automatic Telephone and Electric Co Ltd
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Filing: 1970-02-16
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Granted: 1971-11-30
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Expires: 1990-02-16
Abstract
Abstract A checking and fault-indicating arrangement is provided for four or a larger even number of processors in a data processing system. During a first predetermined period, odd-numbered processors perform a processing operation and the input date applied to one of the odd-numbered processors is also applied to a particular one of the adjacent even-numbered processors and the output of the two processors is compared in a comparator which provides a significant output if one of the processors are faulty. During a second predetermined period, even-numbered processors perform a processing operation and the input data applied to the other adjacent one of the even-numbered processors is also applied to said one odd-numbered processor and the output of the two processors is compared in a second comparator which also provides a significant output if one of the processors is faulty. The significant outputs of the two comparators are applied to an indicating arrangement which indicates the faulty processor.
Inventors
- 👤 Alexander Schroder Philip
- 👤 John Richard Francis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:36
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1629; G06F11/1654; G06F11/1641
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
289 words
In a data processing arrangement a checking and faultindicating arrangement associated with an even number of processors, at least four, comprising a first group of processors, a second group of processors equal in number of said first group of processors, means effective during a first predetermined period for controlling each of the processors of said first group to perform a processing operation, means effective during said first predetermined period for applying the data applied for processing to a processor of said first group to a particular processor of said second group, means effective during a second predetermined period for controlling each of the processors of said second group to perform a processing operation, means effective during said second predetermined period for applying the data applied for processing to a second processor of said second group to said processor of said first group, a first comparator individual to said processor of said first group and to said particular processor of said second group, means effective during said first predetermined period for applying the outputs of said processor of said first group and said particular processor of said second group to said first comparator, a second comparator individual to said processor of said first group and said second processor of said second group, means effective during said second predetermined period for applying the outputs of said processor of said first group and said second processor of said second group to said second comparator whereby a significant output is obtAined from said first and said second comparators if said processor of said first group is faulty and an indicating arrangement to which the significant outputs of said first and second comparators are applied and which give an indication of the faulty processor.
Claim 2
Dependent Claim
289 words
In a data processing arrangement a checking and faultindicating arrangement associated with an even number of processors, at least four, comprising a first group of processors, a second group of processors equal in number of said first group of processors, means effective during a first predetermined period for controlling each of the processors of said first group to perform a processing operation, means effective during said first predetermined period for applying the data applied for processing to a processor of said first group to a particular processor of said second group, means effective during a second predetermined period for controlling each of the processors of said second group to perform a processing operation, means effective during said second predetermined period for applying the data applied for processing to a second processor of said second group to said processor of said first group, a first comparator individual to said processor of said first group and to said particular processor of said second group, means effective during said first predetermined period for applying the outputs of said processor of said first group and said particular processor of said second group to said first comparator, a second comparator individual to said processor of said first group and said second processor of said second group, means effective during said second predetermined period for applying the outputs of said processor of said first group and said second processor of said second group to said second comparator whereby a significant output is obtAined from said first and said second comparators if said processor of said first group is faulty and an indicating arrangement to which the significant outputs of said first and second comparators are applied and which give an indication of the faulty processor.
Claim 3
Dependent Claim
86 words
A checking and fault-indicating arrangement as claimed in claim 1, wherein the outputs of said second processor of said second group and a second processor of the first group are applied to a third comparator individual to said two processors during a predetermined period succeeding said second predetermined period and corresponding to said first predetermined period and if said second processor of said second group is faulty, and significant outputs of said second and third comparators applied to said indicating arrangement will identify the faulty processor.
Claim 4
Dependent Claim
92 words
A checking and fault-indicating arrangement as claimed in claim 1, wherein the processors are arranged in a ring formation and the first group of processors are the odd-numbered processors in the ring and the second group are even-numbered processors, the data applied for processing to an odd-numbered processor during the first predetermined period being also applied to the immediately preceding even-numbered processor in the ring whereas the data applied for processing to the immediately succeeding even-numbered processor in the ring during the second predetermined period is also applied to said odd-numbered processor.
Claim 5
Dependent Claim
57 words
A checking and fault-indicating arrangement as claimed in claim 3, wherein a shift register is associated with each one of the processors and gating arrangements are provided which enable the output of a shift register to be gated into the associated processor and into the immediately preceding processor in the ring during one of the predetermined periods.
Claim 6
Dependent Claim
60 words
A checking and fault-indicating arrangement as claimed in claim 4, wherein gating arrangements are provided for updating during said first predetermined period the data applied to a processor from its associated shift register and for updating during said second predetermined period the data applied to said processor from the shift register associated with the immediate succeeding processor in the ring.
Claim 7
Dependent Claim
87 words
A checking and fault-indicating arrangement as claimed in claim 1, wherein said indicating arrangement comprises two two-state switching devices for each comparator, the switching devices having set and reset sides and a significant output from a comparator sets the first of the associated switching devices, the set output of said first comparator and the set output of said second comparator being applied to an AND circuit, the output of which sets the second of the associated switching devices, the set output of which identifies the faulty processor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-29 | 1975-05-31 | 1975-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-29 | 1979-05-31 | 1979-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-29 | 1983-05-31 | 1983-11-30 | $7700.00 | Window Closed / Lapsed |