Error detection and instruction reexecution device in a data-processing apparatus

Claim 2

A data-processing apparatus for effecting data processing using sequentially controlled processing stages comprising: an addressable memory storing words including information processed in said processing stages and information of a check field representing whether the reexecution should be done for each instruction, circuits connected with said memory for executing processing in accordance with contents stored in said memory, error operation detecting means provided in said circuits for detecting an error operation therein and producing an error signal; a check register connected to said memory to set therein contents of the check field in the words, said register being adapted to provide a signal representing whether the reexecution should be done for each instruction, whether the reexecution should be done for each processing stage or whether the reexecution is impossible, for occurrence of an error operation, and an address control circuit connected with said check register and said detecting means to provide a signal representing the address of words in said memory corresponding to a processing stage in accordance with the signal provided from said check register upon reception of said error signal and to supply it to said memory.

Claim 3

The data-processing apparatus according to claim 1, in which said check register has the function representing whether the reexecution should be done for a series of processing stages upon the occurrence of the error operation.

Claim 4

The data processing apparatus according to claim 1, in which said check register comprises: first, second and third flip-flops adapted successively to be set by the contents of check field of said words every processing stage and to be reset at the last processing stage of one instruction executing sequence, the set outputs of said first and third flip-flop representing that the reexecution is impossible and that the reexecution is being effected, respectively, a fourth flip-flop adapted to be set by the contents of check field of said words every processing stage and to be reset at the termination of the respective processing stages, a first transfer means to transfer the set output of said first flip-flop to said address control circuit, a first AND gate receiving reset outputs of said first and fourth flip-flop and providing at its output side a signal representing a command of the reexecution for each instruction, a second transfer means to transfer the output signal of said first AND gate to said address control circuit, a second AND gate receiving at its input side the reset output of said first flip-flop and a set output of said fourth flip-flop and providing at its output side an output signal representing a command of the reexecution for each processing stage, a third transfer means to transfer said output signal produced from said second AND gate to said address control circuit, and a fourth transfer means to transfer said set output of the third flip-flop to said address control circuit

Claim 5

The data-processing apparatus according to claim 1, further comprising an address evacuation register connected to said address control circuit for evacuating an address signal generated by said address control circuit which will be to the address of said memory and providing it to said address control circuit upon the reexecution.

Claim 6

A data-processing apparatus for effecting execution of instructions using a plurality of micro instructions sequentially controlled comprising: an addressable read only memory storing the micro instructions including at least function field representing processed contents and check field representing information for reexecution, a check register adapted to be set by the contents of check fIeld in said micro instruction, said check register providing a signal representing whether the reexecution should be done for each instruction, whether the reexecution should be done only for micro instructions under error operation, or whether the reexecution is impossible, for occurrence of an error operation, and an address control circuit adapted to represent the address of micro instructions in said read only memory, which is determined by contents of said check register upon occurrence of an error operation.

Claim 7

A data-processing apparatus for effecting execution of instructions using a plurality of micro instructions sequentially controlled comprising: an addressable read only memory storing the micro instructions including at least function field representing processed contents and check field representing information for reexecution, a check register adapted to be set by the contents of check fIeld in said micro instruction, said check register providing a signal representing whether the reexecution should be done for each instruction, whether the reexecution should be done only for micro instructions under error operation, or whether the reexecution is impossible, for occurrence of an error operation, and an address control circuit adapted to represent the address of micro instructions in said read only memory, which is determined by contents of said check register upon occurrence of an error operation.

Claim 8

An apparatus in accordance with claim 5, further including an address evacuation register connected to said address control circuit for evacuating an address signal generated by said address control circuit and transferring said signal, representative of an address in said memory, to said address control circuit upon reexecution.

Claim 9

A data-processing apparatus comprising: a series of sequentially controlled processing stages; an addressable memory for storing instructions including information processed in said processing stages and a check field containing information representing whether an instruction should be reexecuted; a series of processing circuits connected to said memory for executing said instructions in accordance with the contents of said memory, said processing stages including means for detecting an error operation occuring during the execution of said instructions and for producing an error signal in response thereto; a check register, responsive to said error signal and connected to said memory for setting therein the contents of said check field, said check register including first means, responsive to a first predetermined condition of said check field, for providing a first signal representative of whether each instruction should be reexecuted, second means responsive to a second predetermined condition of said check field, for providing s second signal representative of whether each processing stage should be reexecuted, and third means, responsive to a third predetermined condition of said check field, for providing a third signal representative of whether reexecution of said instructions is impossible; and an address control circuit, connected to said check register and said error operation detecting means and responsive to the outputs thereof, for providing a signal representative of the address of data in said memory corresponding to a particular processing stage for supplying said address location to said memory.

Claim 10

A data-processing apparatus comprising: a series of sequentially controlled processing stages; an addressable memory for storing instructions including information processed in said processing stages and a check field containing information representing whether an instruction should be reexecuted; a series of processing circuits connected to said memory for executing said instructions in accordance with the contents of said memory, said processing stages including means for detecting an error operation occuring during the execution of said instructions and for producing an error signal in response thereto; a check register, responsive to said error signal and connected to said memory for setting therein the contents of said check field, said check register including first means, responsive to a first predetermined condition of said check field, for providing a first signal representative of whether each instruction should be reexecuted, second means responsive to a second predetermined condition of said check field, for providing s second signal representative of whether each processing stage should be reexecuted, and third means, responsive to a third predetermined condition of said check field, for providing a third signal representative of whether reexecution of said instructions is impossible; and an address control circuit, connected to said check register and said error operation detecting means and responsive to the outputs thereof, for providing a signal representative of the address of data in said memory corresponding to a particular processing stage for supplying said address location to said memory.

Claim 11

An apparatus in accordance with claim 7, wherein said check register comprises: first, second and third flip-flops successively set by the contents of said check field and reset at the last processing stage of one instruction executing sequence, the said outputs of said first and third flip-flops, representing that reexecution is impossible and that reexecution is being effected, respectively; a fourth flip-flop adapted to be set by the contents of said check field during every processing stages and to be reset at the termination of the respective processing stages; a first transfer means for transferring the set output of said first flip-flop to said address control circuit; a first AND gate responsive to the reset outputs of said first and fourth flip-flops for providing a signal representing the reexecution command for each instruction; second transfer means for transferring the output of said first AND gate to said address control circuit; a second AND gate responsive to the reset output of said first flip-flop and the set output of said fourth flip-flop for providing a signal representative of the reexecution of each processing stage; third transfer means for transferring the output of said second AND gate to said address control circuit; and fourth transfer means for transferring the set output of said third flip-flop to said address control circuit.