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US3618040A
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Memory control apparatus in multiprocessor system
Assignee: Hitachi Ltd
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Filing: 1969-09-17
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Granted: 1971-11-02
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Expires: 1989-09-17
Abstract
Abstract Information transferred from a main memory with energy block is stored in two high-speed buffer memories provided in two respective central processors, and the address signals of said information are held in a register. Upon access of one of said central processors to the main memory, address signals therefrom are compared with the address signal held in said register by a first compare circuit, and thus if there is any coincident address signal, then access to the buffer memory is permitted. When the other central processor effects ''''write-in'''' with respect to the main memory, an address signal forwarded by said other central processor is compared with the address signals held in said register by a second compare circuit, and thus if there is any coincident address signal, then the corresponding information is made invalid so as to avoid disagreement between the contents of the main memory and buffer memories.
Inventors
- 👤 Shoji Iwamoto
- 👤 Hisashi Horikoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:00
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
153 words
A memory control apparatus in a multiprocessor system comprising: a plurality of central processors; a main memory to which said pLurality of central processors are commonly accessible; a plurality of buffer memories each provided in correspondence to each central processor respectively, for reading out and storing information stored in its corresponding main memory by a predetermined amount; and a plurality of memory control means each provided in correspondence to each said buffer memory respectively, for controlling write-in and readout information to its corresponding buffer memory, wherein each of said memory control means comprises means for detecting whether or not an information required by its corresponding central processor is stored in the corresponding buffer memory as valid information thereof, and means for detecting whether or not an information to be rewritten in the main memory by any of the other central processors has been stored in said buffer memory of the corresponding central processor.
Claim 2
Dependent Claim
153 words
A memory control apparatus in a multiprocessor system comprising: a plurality of central processors; a main memory to which said pLurality of central processors are commonly accessible; a plurality of buffer memories each provided in correspondence to each central processor respectively, for reading out and storing information stored in its corresponding main memory by a predetermined amount; and a plurality of memory control means each provided in correspondence to each said buffer memory respectively, for controlling write-in and readout information to its corresponding buffer memory, wherein each of said memory control means comprises means for detecting whether or not an information required by its corresponding central processor is stored in the corresponding buffer memory as valid information thereof, and means for detecting whether or not an information to be rewritten in the main memory by any of the other central processors has been stored in said buffer memory of the corresponding central processor.
Claim 3
Dependent Claim
162 words
A memory control apparatus in a multiprocessor system according to claim 1, wherein each of said buffer memories comprises a plurality of sectors and each of said memory control means comprises register means for holding the address signals of that information in the main memory which is stored in the respective sectors of the buffer memories, a first compare means for comparing address signal imparted thereto by said corresponding central processor and the address signals corresponding to the respective sectors held in said register means and a second compare means for comparing address signals of information to be rewritten in the main memory by any of the other central processors and the address signals corresponding to the respective sectors held in said register means to thereby make invalid any sector in said register means the address signal in which conforms to the address signal of said information of sectors which contains information to be rewritten by any of the other central processors.
Claim 4
Dependent Claim
57 words
A memory control apparatus in a multiprocessor system according to claim 1, further comprising an address bus to which are passed the address signals of certain information to be rewritten in the main memory by the respective central processors, so that those address signals are transmitted therethrough to said memory control means of the other central processors.
Claim 5
Dependent Claim
94 words
A memory control apparatus in a multiprocessor system according to claim 2, wherein said first compare means comprises a first compare circuit for comparing an address signal forwarded thereto by said corresponding central processors with the respective address signals corresponding to the respective sectors stored in said register means so as to provide a signal representing a sector whose address signal is coincident with said address signal from said corresponding central processor, and an encoder for converting the signal representing said coincident sector to the address corresponding to the sector in the buffer memory.
Claim 6
Dependent Claim
116 words
A memory control apparatus in a multiprocessor system according to claim 2, wherein said register means comprises registers each including a sector portion for storing the upper part of the address signal of information stored in the predetermined sector of the buffer memory and a block validity portion indicating whether valid information is stored in the respective blocks in each sector, means for setting in said sector portion the upper part of the address signal of information read out of the main memory, and decoder means for converting the lower part of said address signal to a signal representing a block in each sector so as to set the converted signal in said block validity portion.
Claim 7
Dependent Claim
63 words
A memory control apparatus in a multiprocessor system according to claim 5, wherein said register means further includes gate means for detecting the signal representing the validity of the block stored in said block validity portion by using as gate signals the signal representing the coincident sector generated by said first compare means and the signal representing the block generateD by said decoder.
Claim 8
Dependent Claim
108 words
A memory control apparatus in multiprocessor system according to claim 5, wherein said second compare means comprises a comparator for comparing the upper part of the address signal forwarded by the other central processors with the respective address signals corresponding to the respective sectors stored in said sector portion so as to provide a signal representing the coincident sector, and decoder means for converting the lower part of the address signal forwarded by said other central processors to a signal representing the block so as to reset the bit of said block validity portion corresponding to said block under the control of said signal representing the coincident sector.
Claim 9
Dependent Claim
111 words
A memory control apparatus according to claim 4, wherein said register means comprises registers, each including a separate portion for storing the upper part of the address signal of information stored in the predetermined sector of the buffer memory and a block validity portion indicating whether valid information is stored in the respective blocks in each sector, means for setting in each sector portion the upper part of the address signal of information readout of the main memory, and decoder means for converting the lower part of said address signal to a signal representing the block in each sector, so as to set the converted signal in said block validity portion.
Claim 10
Dependent Claim
59 words
A memory control apparatus according to claim 8, wherein said register means further includes gate means for detecting the signal representing the validity of the block stored in said block validity portion by using as gate signals the signal representing the coincident sector generated by said first compare means and the signal representing the block generated by said decoder.
Claim 11
Dependent Claim
103 words
An apparatus according to claim 9, wherein said first compare circuit comprises a first compare circuit comparator for comparing the upper part of the address signal transferred from the central processor thereto and each of the address signals set in the respective sector portions of said registers in said register means, and providing output signals representative of coincidence therebetween, a gate circuit for gating the respective output signals provided by said comparator with signals representing the validity of the respective sector portions, and a register for temporarily storing the output of said gate circuit and for transferring the contents thereof to said encoder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-01 | 1975-05-03 | 1975-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-01 | 1979-05-03 | 1979-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-01 | 1983-05-03 | 1983-11-02 | $7700.00 | Window Closed / Lapsed |