Digital data communication multiple line control

Claim 2

Apparatus for controlling the transfer of digitized data between a digital processor and a plurality of separate transmission lines where the transmission lines may be terminated by different types of terminal units which transmit and receive data serially at a number of different predetermined bit rates, said apparatus comprising storage means for storing a separate control word for each transmission line, a controL register for storing one such control word, clock means for simultaneously generating a plurality of periodic output signals of different frequencies, an input register, a logic network having inputs coupled respectively to the control register, the input register and the output signals of the clock means, the logic network having two outputs means continuously transferring each of the control words in sequence on successive clock cycles of the highest frequency signal of said clock source from the storage means to the control register, means coupling the output of each of the transmission line terminal units in succession to the input register in synchronism with said transfer of the control words, means coupling one output of the logic network back to the storage means, said coupling means transferring said output to each of the control word storage locations in the storage means in timed sequence in synchronism with said highest frequency clock signal, and means simultaneously coupling the other output of the logic circuit to successive ones of the transmission line units in the same sequence.

Claim 3

Apparatus as defined in claim 1, further including a buffer register, means coupling the processor to the buffer register for transferring information signals between the processor and the buffer register, the buffer register having a control portion for storing a control signal, a data portion for storing a data signal, and an address portion for storing an address signal identifying a particular one of the transmission line terminal units and the associated control word in the storage means, means responsive to the address signal stored in the address portion of the buffer register for identitying the addressed control word as it is being transferred by said transferring means from the storage means to the control register, means responsive to a first condition of the control signal established by the control portion of the buffer register for transferring the data signal stored in the data portion of the buffer register to a selected portion of the particular control word identified by said contents of control signal, and means responsive to a second condition of the control signal established by the control portion of the contents of the buffer register for transferring a selected portion of the contents of the buffer register from the particular control word identified by said identifying means to the data portion of the buffer register.

Claim 4

Apparatus as defined in claim 1 wherein the logic network includes a constant generator for generating a binary coded output signal having a value determined by the value of a coded input, each control word having a first portion identifying the type of transmission line terminal unit and a second portion including a counter for timing bit intervals, means responsive to a control word in said control register for coupling the first portion of the control word in the control register to the constant generator for generating a selected constant, means responsive to the second portion of the control word in the control register when in a first predetermined count condition for transferring the output of the constant generator to the second portion of the control word as it is restored to the storage means from the control register via said logic network, means in the logic network for decrementing the second portion of the control word in response to an input signal and means responsive to the first portion of the control word in the control register for selectively gating one of said periodic outputs from the clock means to the signal input of the decrementing means to activate the decrementing means periodically at the selected clock output frequency.

Claim 5

Apparatus as defined in claim 3, wherein said constant generator further includes means responsive to the outputs from the clock means for periodically changing the value of said binary coded output signal selected by the constant generator in response to the first portion of a coded word, the value of the output signal being changed by a predetermined increment, the interval at which the output value is changed being selected in response to the value of said first portion of the control word.

Claim 6

Apparatus as defined in claim 1, wherein each control word has first and second character storing fields, a type field an operation control field, and a timing field, the logic network including means responsive to the operation control field of a control word in the control register for identifying a transmit operation, the logic network including a translator circuit coupled to the first character field of the control register and responsive to the type field in the control register for generating an output that is a selectably modified version of the input depending on the particular type field present, and means activating the translator circuit condition of) when the control field is in a predetermined condition, the first character field contains a data character, and the second character field is empty, the output of the translator being connected by the switching means to the second character field of the control word in the storage means, whereby the translator transfers a character in the first character field in selectably modified form to the second character field.

Claim 7

A data communication control unit for interconnecting a plurality of different types of data communication units with a digital processor, comprising a plurality of separate adapter units, each unit providing an interface with one of said data communication units, each adapter unit including an output register for storing an output data bit to be transmitted by the associated communication unit and control bits, storage means for storing a group of control words, there being one control word for each adapter unit, a control register, means for continuously transferring each of the control words in succession out of the storage means into the control register at fixed equal time intervals, an input register, means synchronized with said transferring means for continuously coupling the input register to the output from each of the adapter units in succession, a buffer register, means coupling the processor to the buffer register for transferring control and data bits between the processor and the buffer register, means responsive to the buffer register for modifying a selected control word with a portion of the contents of the buffer register when the control word is transferred from the storage means to the control register, a clock counter having a plurality of periodic outputs, each output period being a different integral multiple of the period at which a particular control word is transferred out of the storage means, logic gating means coupled to the control register, the input register, and the clock counter for providing output signals to the storage means and to the adapter units, means synchronized with said transferring means for coupling one output from the logic gating means successively to each of the positions in the storage means, and means synchronized with said transferring means for coupling another output from the logic gating means successively to the output register in each of the associated adapter units.

Claim 8

A data communication control unit for interconnecting a plurality of different types of data communication units with a digital processor, comprising a plurality of separate adapter units, each unit providing an interface with one of said data communication units, each adapter unit including an output register for storing an output data bit to be transmitted by the associated communication unit and control bits, storage means for storing a group of control words, there being one control word for each adapter unit, a control register, means for continuously transferring each of the control words in succession out of the storage means into the control register at fixed equal time intervals, an input register, means synchronized with said transferring means for continuously coupling the input register to the output from each of the adapter units in succession, a buffer register, means coupling the processor to the buffer register for transferring control and data bits between the processor and the buffer register, means responsive to the buffer register for modifying a selected control word with a portion of the contents of the buffer register when the control word is transferred from the storage means to the control register, a clock counter having a plurality of periodic outputs, each output period being a different integral multiple of the period at which a particular control word is transferred out of the storage means, logic gating means coupled to the control register, the input register, and the clock counter for providing output signals to the storage means and to the adapter units, means synchronized with said transferring means for coupling one output from the logic gating means successively to each of the positions in the storage means, and means synchronized with said transferring means for coupling another output from the logic gating means successively to the output register in each of the associated adapter units.

Claim 9

A time-shared system for controlling transfer of digital data between a common source over a plurality of transmission lines where different data transfer rates may be required on each line, said system comprising: storage means for storing a plurality of digital control words, each word having a character field, a timing field, and a type field, a clocking circuit for generating a plurality of periodic output signals of different frequencies that are integral multiples of each other, a time-shared control network, switching means synchronized with the highest frequency output of the clocking circuit for connecting each of the digital control words in the storage means to the control network in repetitive sequence, and connecting each of the transmIssion lines to the control network in the same repetitive sequence, whereby one of the control words and an associated one of the transmission lines are connected at a time to the control network, the control network including means responsive to a predetermined state of the timing field and to the type field of each control word when it is connected to the control network for setting the timing field of the control word to some selected constant, means responsive to the type field and the outputs of the clocking circuit for periodically counting the timing field of each control word when it is connected to the control network, the counting period for the timing field of each control word being determined by the state of the type field for that control word, and means responsive to the timing field in each control word when counted to a predetermined state and connected to the control network for transferring date between the character field of the control word and corresponding transmission line.

Claim 10

A time-shared system for controlling transfer of digital data between a common source over a plurality of transmission lines where different data transfer rates may be required on each line, said system comprising: storage means for storing a plurality of digital control words, each word having a character field, a timing field, and a type field, a clocking circuit for generating a plurality of periodic output signals of different frequencies that are integral multiples of each other, a time-shared control network, switching means synchronized with the highest frequency output of the clocking circuit for connecting each of the digital control words in the storage means to the control network in repetitive sequence, and connecting each of the transmIssion lines to the control network in the same repetitive sequence, whereby one of the control words and an associated one of the transmission lines are connected at a time to the control network, the control network including means responsive to a predetermined state of the timing field and to the type field of each control word when it is connected to the control network for setting the timing field of the control word to some selected constant, means responsive to the type field and the outputs of the clocking circuit for periodically counting the timing field of each control word when it is connected to the control network, the counting period for the timing field of each control word being determined by the state of the type field for that control word, and means responsive to the timing field in each control word when counted to a predetermined state and connected to the control network for transferring date between the character field of the control word and corresponding transmission line.

Claim 11

Apparatus as defined in claim 7 wherein said means for setting the timing field to some selected constant further includes means responsive to the clocking circuit and the type field of the control word for periodically changing the value of the constant at selected settings.

Claim 12

A time-shared timing system comprising: storage means for storing a plurality of digital control words, each digital control word having a timing field, a type field, a clocking circuit for generating a plurality of periodic output signals of different frequencies that are integral multiples of each other, a time-shared control network, switching means synchronized with the highest frequency output of the clocking circuit for connecting each of the digital control words in the storage means to the control network in repetitive sequence at fixed equal time intervals, the control network including means responsive to a predetermined state of the timing field and to the type field of each digital control word when it is connected to the control network for setting the timing field of the control word to some selected constant, and means responsive to the type field and the outputs of the clocking circuit for periodically counting the timing field of each control word when it is connected to the control network, the counting period for the timing field of each control word being determined by the state of the type field for that control word.

Claim 13

A time-shared timing system comprising: storage means for storing a plurality of digital control words, each digital control word having a timing field, a type field, a clocking circuit for generating a plurality of periodic output signals of different frequencies that are integral multiples of each other, a time-shared control network, switching means synchronized with the highest frequency output of the clocking circuit for connecting each of the digital control words in the storage means to the control network in repetitive sequence at fixed equal time intervals, the control network including means responsive to a predetermined state of the timing field and to the type field of each digital control word when it is connected to the control network for setting the timing field of the control word to some selected constant, and means responsive to the type field and the outputs of the clocking circuit for periodically counting the timing field of each control word when it is connected to the control network, the counting period for the timing field of each control word being determined by the state of the type field for that control word.

Claim 14

In a digital processing system apparatus for generating a plurality of variable timeout intervals on a time-shared basis, comprising storage means for storing a plurality of separate control words, there being one coded word for each timeout interval being generated, a control register, a timer circuit for generating a plurality of periodic output signals of different frequencies, means synchronized with the highest frequency output of the timer circuit for cycling each of the control words in sequence into the control register and back into the storage means, means responsive to a first portion of a control word when in the register for selecting particular outputs from said timer, means synchronized with the selected outputs for counting down a second portion of the control word periodically as the control word is cycled through the register, and means responsive to a predetermined count condition the second portion of a control word in the register for generating an output signal indicating the completion of one of said timeout intervals.

Claim 15

In a digital processing system apparatus for generating a plurality of variable timeout intervals on a time-shared basis, comprising storage means for storing a plurality of separate control words, there being one coded word for each timeout interval being generated, a control register, a timer circuit for generating a plurality of periodic output signals of different frequencies, means synchronized with the highest frequency output of the timer circuit for cycling each of the control words in sequence into the control register and back into the storage means, means responsive to a first portion of a control word when in the register for selecting particular outputs from said timer, means synchronized with the selected outputs for counting down a second portion of the control word periodically as the control word is cycled through the register, and means responsive to a predetermined count condition the second portion of a control word in the register for generating an output signal indicating the completion of one of said timeout intervals.

Claim 16

Apparatus as defined in claim 10 wherein said last-named means includes means for setting a third portion of the control word to a predetermined value to indicate that the timeout interval is complete.

Claim 17

Apparatus as defined in claim 11 further including a digital processor, means for setting the first and second portion of any selected one of the control words in the storage register from the processor, and means responsive to said predetermined value of the third portion of any of said control wordS for signaling the processor that a particular timeout interval is complete.