Patent US3617895A successfully refreshed from Google Patents.
US3617895A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multifrequency receiver with automatic channel selection and priority channel monitoring
Assignee: Motorola Solutions Inc
•
Filing: 1969-08-08
•
Granted: 1971-11-02
•
Expires: 1989-08-08
Abstract
Abstract A switching system for a receiver with a plurality of local oscillators for operating on different channels renders the oscillators operative in turn, with the switching system being latched when a carrier is received to hold the receiver on the channel having the carrier. One channel is designated a priority channel, and the oscillator for that channel is operated at recurring short periods when another channel is being received in order to continually sample the priority channel. If a signal is detected on the priority channel during the sampling interval, the receiver locks onto the priority channel until the carrier on that channel terminates. The length of time that the priority channel is sampled during reception on another channel is variable in that there are no circuit time constants which force the circuitry to return to the nonpriority channel after a fixed length of time. When the system samples the priority channel, it stays on the priority channel until noise is detected. If a marginal signal is on the priority channel or if a statistical noise null is present, the sample length is extended until noise reappears on the priority channel.
Inventors
- 👤 Stanley J Tomsa
- 👤 David F Willard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 10:58
CPC Classifications
H; H04; H04B; H04B7/00; H04B7/02; H04B7/12
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
404 words
A radio receiver of the superheterodyne type for receiving signals on a predetermined number of channels, one of which is designated a priority channel, said receiver having a channel scanning and priority channel monitoring circuit including in combination: mixing means operative to provide reception by said radio receiver on said different channels; oscillator means connected to the mixing means for providing output signals to the mixing means at different frequencies corresponding to said different channels; switching means having at least first and second conditions of operation coupled to the oscillator means for controlling the output frequency of the oscillator means in accordance with the condition of operation of the switching means, one of the conditions of operation of the switching means corresponding to the priority channel; first timing control circuit means having a cycle of operation and connected with the switching means for controlling the durations of time of the conditions of operation of the switching means in accordance with said cycle of operation, means for detecting the presence of a received signal at the output of the mixing means; second timing control circuit means controlled by the outputs of the switching means and the signal detecting means for causing the cycle of operation of the first timing control circuit means to be at a first predetermined time pattern when no signals are present on any of the channels and to be at a second predetermined time pattern when a signal is present on a nonpriority channel; means responsive to the outputs of the switching means and the signal detecting means for disabling control of the switching means by the first timing control circuit when the switching means is set to the condition corresponding to the priority channel at the time the signal detecting means provides an output indicative of the presence of a received signal; and means responsive to the output of the switching means when the switching means is set to the condition of operation corresponding to a priority channel, and further responsive to the output of the signal detecting means for varying the second predetermined time pattern with respect to the duration of time that the switching means is set to the condition of operation corresponding to the priority channel, said duration of time being dependent upon the length of time that a signal is sensed by the detecting means during the priority channel condition of operation of the switching means.
Claim 2
Dependent Claim
404 words
A radio receiver of the superheterodyne type for receiving signals on a predetermined number of channels, one of which is designated a priority channel, said receiver having a channel scanning and priority channel monitoring circuit including in combination: mixing means operative to provide reception by said radio receiver on said different channels; oscillator means connected to the mixing means for providing output signals to the mixing means at different frequencies corresponding to said different channels; switching means having at least first and second conditions of operation coupled to the oscillator means for controlling the output frequency of the oscillator means in accordance with the condition of operation of the switching means, one of the conditions of operation of the switching means corresponding to the priority channel; first timing control circuit means having a cycle of operation and connected with the switching means for controlling the durations of time of the conditions of operation of the switching means in accordance with said cycle of operation, means for detecting the presence of a received signal at the output of the mixing means; second timing control circuit means controlled by the outputs of the switching means and the signal detecting means for causing the cycle of operation of the first timing control circuit means to be at a first predetermined time pattern when no signals are present on any of the channels and to be at a second predetermined time pattern when a signal is present on a nonpriority channel; means responsive to the outputs of the switching means and the signal detecting means for disabling control of the switching means by the first timing control circuit when the switching means is set to the condition corresponding to the priority channel at the time the signal detecting means provides an output indicative of the presence of a received signal; and means responsive to the output of the switching means when the switching means is set to the condition of operation corresponding to a priority channel, and further responsive to the output of the signal detecting means for varying the second predetermined time pattern with respect to the duration of time that the switching means is set to the condition of operation corresponding to the priority channel, said duration of time being dependent upon the length of time that a signal is sensed by the detecting means during the priority channel condition of operation of the switching means.
Claim 3
Dependent Claim
58 words
The combination according to claim 1 wherein the switching means is a trigger circuit providing a priority and a nonpriority output and wherein the first timing control circuit includes a first timing capacitor having a charging path and a discharge path therefor, the charge on the timing capacitor being used to control the operation of the trigger circuit.
Claim 4
Dependent Claim
33 words
The combination according to claim 2 wherein the trigger circuit provides a nonpriority output when the first timing capacitor is charged and provides a priority output when the first timing capacitor is discharged.
Claim 5
Dependent Claim
64 words
The combination according to claim 2 wherein a plurality of nonpriority channels are provided and further including means responsive to the nonpriority output of the trigger circuit to sequentially control the oscillator means to provide output frequencies corresponding to the different nonpriority channels during said nonpriority output, the sequential control means being disabled in response to detection of a signal by the detecting means.
Claim 6
Dependent Claim
74 words
The combination according to claim 2 wherein the disabling means includes an inhibit gate and control switching means in the charging path of the first timing capacitor and operated in response to the output of the signal detecting means, wherein the output of the signal detecting means is applied through said inhibit gate to the control switching means with the inhibit input of said inhibit gate being obtained from the second timing control means.
Claim 7
Dependent Claim
40 words
The combination according to claim 5 wherein the control switching means is operated to complete the charging path for the first timing capacitor in response to an output from the signal detecting means indicating the absence of a detected signal.
Claim 8
Dependent Claim
101 words
The combination according to claim 5 wherein the second timing control circuit includes a second timing capacitor provided with a first charging path from the nonpriority output of the trigger circuit, and means responsive to the output of the signal detecting means for disabling said first charging path in response to detection of a signal by the detecting means, the charge on the second timing capacitor controlling the length of time an inhibit input is applied to the inhibit gate following the time the trigger circuit is switched from the nonpriority to the priority state by the first timing control circuit.
Claim 9
Dependent Claim
86 words
The combination according to claim 7 further including a second charging path for the second timing capacitor and means responsive to the output of the signal detecting means and the priority output of the trigg circuit for completing the second charging path whenever the trigger circuit provides a priority output and the detecting means detects the presence of a received signal to control the length of time an inhibit input is applied to the inhibit gate following termination of a detected signal on the priority channel.
Claim 10
Dependent Claim
48 words
The combination according to claim 8 wherein the time constants of the first charging path for the second timing capacitor permit the second timing capacitor to be fully charged to a predetermined value in the absence of a detected signal during the nonpriority output of the trigger circuit.
References Cited (Backward Citations)
US3470481A
Cited
US3497813A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-01 | 1975-05-03 | 1975-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-01 | 1979-05-03 | 1979-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-01 | 1983-05-03 | 1983-11-02 | $7700.00 | Window Closed / Lapsed |