Digital voltmeters

Claim 2

A dual ramp digital voltmeter responsive to an input voltage, said meter being of the type comprising an integrating means, a source of a reference voltage opposing the input voltage, a source of clock pulses, a pulse counter, control logic means responsive to said pulse counter for causing the input voltage initially to be applied to ramp up the integrating means from a datum level for a standard number of clock pulses and then for causing the opposing reference voltage to be applied to ramp down the integrating means during a measuring interval and for simultaneously causing the pulse counter to count the clock pulses, and means responsive to the return of said integrating means to datum level for terminating the measuring interval and pulse counting, wherein the improvement comprises dividing means interposed between said source of clock pulses and said pulse counter for dividing the pulse rate of pulses supplied to said counter, and means for varying the divisor introduced by said dividing means to vary selectively the repetition rate of the pulses supplied to the counter.

Claim 3

A voltmeter according to claim 1, wherein the said means for varying the divisor is responsive to the control logic to change the divisor at the instant of changing from ramp up to ramp down.

Claim 4

A voltmeter according to claim 2, further comprising range-setting means having a plurality of settings, said means for varying the divisor being further responsive to the range-setting means to provide different divisors in at least one of the ramp up and ramp down intervals for different ones of said settings, thereby to provide in the different settings different ratios of the repetition rates of the pulses supplied to the counter during the ramp up and ramp down intervals.

Claim 5

A voltmeter according to claim 1, wherein said means for varying the diVisor is responsive to the pulse counter to change the divisor at the instant of at least one breakpoint corresponding to a particular count in the counter.

Claim 6

A voltmeter according to claim 4, comprising means for restricting changes of the divisor to a particular one of the ramp up and ramp down intervals.

Claim 7

A voltmeter according to claim 4, comprising means for restricting changes of the divisor to the ramp down interval.

Claim 8

A voltmeter according to claim 4, comprising means for selectively varying the particular count.

Claim 9

In a dual ramp digital voltmeter responsive to an input voltage and comprising an integrating means, a source of a reference voltage opposing the input voltage, a source of clock pulses, a pulse counter and control logic responsive thereto to cause the input voltage initially to be applied to ramp up the integrating means from a datum level for a standard number of clock pulses and then to cause the opposing reference voltage to be applied to ramp down the integrating means during a measuring interval and simultaneously to cause the pulse counter to count the clock pulses and means responsive to the integrating means returning to datum level to terminate the measuring interval and pulse counting, the improvement consisting in means responsive to a particular count being held in the pulse counter to alter the repetition rate of the pulses supplied to the counter.

Claim 10

In a dual ramp digital voltmeter responsive to an input voltage and comprising an integrating means, a source of a reference voltage opposing the input voltage, a source of clock pulses, a pulse counter and control logic responsive thereto to cause the input voltage initially to be applied to ramp up the integrating means from a datum level for a standard number of clock pulses and then to cause the opposing reference voltage to be applied to ramp down the integrating means during a measuring interval and simultaneously to cause the pulse counter to count the clock pulses and means responsive to the integrating means returning to datum level to terminate the measuring interval and pulse counting, the improvement consisting in means responsive to a particular count being held in the pulse counter to alter the repetition rate of the pulses supplied to the counter.

Claim 11

An analog-to-digital converter comprising the combination of an integrating circuit having an input; a source of clock pulses; means for counting clock pulses from said source of clock pulses; a reference signal source; logic circuit means, including said means for counting clock pulses, for applying an analog signal to the input of said integrating circuit to cause said integrating circuit to ramp in a first direction for a selectable predetermined interval of time, and for subsequently applying the signal from said reference signal source to the input of said integrating circuit to cause said integrating circuit to ramp in a second direction to a datum level; means in said logic circuit means for causing said means for counting clock pulses to measure the time to ramp in said second direction; means responsive to the arrival of said ramp in said second direction at said datum level for providing, at the time of the arrival, the accumulated total in said means for counting clock pulses as a digital output representative of the value of the analog signal; and switch means for selectably altering the total number of pulses from said source of clock pulses needed to determine the interval of time occupied by said ramp in said first direction and for selectably altering the rate at which pulses are delivered from said source of clock pulses to said means for counting during the interval of time occupied by said ramp in said second direction.

Claim 12

An analog-to-digital converter comprising the combination of an integrating circuit having an input; a source of clock pulses; means for counting clock pulses from said source of clock pulses; a reference signal source; logic circuit means, including said means for counting clock pulses, for applying an analog signal to the input of said integrating circuit to cause said integrating circuit to ramp in a first direction for a selectable predetermined interval of time, and for subsequently applying the signal from said reference signal source to the input of said integrating circuit to cause said integrating circuit to ramp in a second direction to a datum level; means in said logic circuit means for causing said means for counting clock pulses to measure the time to ramp in said second direction; means responsive to the arrival of said ramp in said second direction at said datum level for providing, at the time of the arrival, the accumulated total in said means for counting clock pulses as a digital output representative of the value of the analog signal; and switch means for selectably altering the total number of pulses from said source of clock pulses needed to determine the interval of time occupied by said ramp in said first direction and for selectably altering the rate at which pulses are delivered from said source of clock pulses to said means for counting during the interval of time occupied by said ramp in said second direction.