Patent US3614741A successfully refreshed from Google Patents.
US3614741A
Expired / Lapsed
US
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Data processing system with instruction addresses identifying one of a plurality of registers including the program counter
Assignee: Digital Equipment Corp
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Filing: 1970-03-23
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Granted: 1971-10-19
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Expires: 1990-03-23
Abstract
Abstract A data processing system processor unit including memory addressing circuits. Operand addresses for identifying data storage locations comprise operand address mode and register selection bits. One of a plurality of registers in the processor unit, which includes the program counter, is selected by decoding the register selection bits. The selected register contents are transferred to the processor unit as data, data addresses or addresses of intermediate storage locations containing data addresses to provide direct, indirect or double deferred addressing. Data or data addresses interleaved with or obtained from information interleaved with instructions are obtained by selecting the program counter. This provides immediate, absolute, relative and deferred relative addressing. The selected register contents are modified if certain address modes are used. A given operation code can be combined with one or two operand addresses in order that each instruction can obtain data from locations in the most efficient manner.
Inventors
- 👤 Harold L Mcfarland Jr
- 👤 James F O'loughlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:36
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/355; G06F9/32; G06F9/322; G06F9/324
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
135 words
A data processing system including a plurality of addressed locations in a processor unit for processing information stored at addressed locations in response to instructions with address portions, said processor unit comprising: A. a plurality of addressed storage registers constituting additional addressed locations, each of said instructions having an address portion defining only one of said registers, and one of said registers being a program counter for controlling the processor unit, B. a transfer unit coupled to the address locations, and C. a control unit including: 1. a register selector responsive to one of the instructions for selecting the register addressed by the instruction address portion, and 2. a transfer control unit responsive to said register selector for connecting said transfer unit to said selected register to convey information to or from said selected register.
Claim 2
Dependent Claim
135 words
A data processing system including a plurality of addressed locations in a processor unit for processing information stored at addressed locations in response to instructions with address portions, said processor unit comprising: A. a plurality of addressed storage registers constituting additional addressed locations, each of said instructions having an address portion defining only one of said registers, and one of said registers being a program counter for controlling the processor unit, B. a transfer unit coupled to the address locations, and C. a control unit including: 1. a register selector responsive to one of the instructions for selecting the register addressed by the instruction address portion, and 2. a transfer control unit responsive to said register selector for connecting said transfer unit to said selected register to convey information to or from said selected register.
Claim 3
Dependent Claim
27 words
a transfer control unit responsive to said register selector for connecting said transfer unit to said selected register to convey information to or from said selected register.
Claim 4
Dependent Claim
27 words
a transfer control unit responsive to said register selector for connecting said transfer unit to said selected register to convey information to or from said selected register.
Claim 5
Dependent Claim
63 words
A data processing system as recited in claim 1 wherein each instruction address portion defines an address mode and a register address, said register selector being responsive to the register address for selecting said register and said control unit additionally comprising an address mode controller responsive to the address mode for modifying the utilization of the selected register contents by said processor unit.
Claim 6
Dependent Claim
21 words
a timing unit responsive to the timing control signal for causing said decoder to generate first and second address signals sequentially,
Claim 7
Dependent Claim
21 words
a timing unit responsive to the timing control signal for causing said decoder to generate first and second address signals sequentially,
Claim 8
Dependent Claim
17 words
an instruction decoder responsive to instructions for identifying those instructions with address mode and register selection portions,
Claim 9
Dependent Claim
17 words
an instruction decoder responsive to instructions for identifying those instructions with address mode and register selection portions,
Claim 10
Dependent Claim
20 words
a register selector responsive to said instruction decoder and an instruction register address portion for selecting any of said registers,
Claim 11
Dependent Claim
20 words
a register selector responsive to said instruction decoder and an instruction register address portion for selecting any of said registers,
Claim 12
Dependent Claim
33 words
a register selector responsive to said timing unit and said instruction decoder for selecting the registers addressed by said instruction address portion as first and second of said addressed registers in sequence, and
Claim 13
Dependent Claim
33 words
a register selector responsive to said timing unit and said instruction decoder for selecting the registers addressed by said instruction address portion as first and second of said addressed registers in sequence, and
Claim 14
Dependent Claim
51 words
A data processing system as recited in claim 2 for responding to a first instruction address mode, said address mode controller and said transfer control unit being responsive to the first address mode for connecting said transfer unit to said selected register for conveying the selected register contents as the information.
Claim 15
Dependent Claim
79 words
A data processing system as recited in claim 2 for responding to a second instruction address mode wherein: A. said address mode controller and said transfer control unit are responsive to the second address mode for connecting said transfer unit to a second location defined by the selected register contents for conveying the information to or from the second location, and B. said transfer unit includes means responsive to said address mode controller for incrementing the selected register contents.
Claim 16
Dependent Claim
23 words
a transfer control unit responsive to said register selector for connecting said transfer unit to said selected registers in sequence to convey information.
Claim 17
Dependent Claim
23 words
a transfer control unit responsive to said register selector for connecting said transfer unit to said selected registers in sequence to convey information.
Claim 18
Dependent Claim
34 words
A transfer unit including gating means and an arithmetic unit responsive to said instruction decoder for modifying data in accordance with the instruction, said gating means coupling said transfer unit to an addressed location,
Claim 19
Dependent Claim
34 words
A transfer unit including gating means and an arithmetic unit responsive to said instruction decoder for modifying data in accordance with the instruction, said gating means coupling said transfer unit to an addressed location,
Claim 20
Dependent Claim
15 words
an address mode controller responsive to said instruction decoder and the address mode portion, and
Claim 21
Dependent Claim
15 words
an address mode controller responsive to said instruction decoder and the address mode portion, and
Claim 22
Dependent Claim
85 words
A data processing system as recited in claim 2 for responding to a third instruction address mode wherein: A. said transfer unit includes means responsive to said address mode controller and said register selector for immediately decrementing the selected register contents, and B. said address mode controller and said transfer control unit are responsive to the third address mode for connecting said transfer unit to a second location defined by the decremented selected register contents for conveying the information to or from the second location.
Claim 23
Dependent Claim
109 words
A data processing system as recited in claim 2 for responding to a fourth instruction address mode and related index value wherein: A said transfer unit includes an adder unit, B. said address mode controller, said register selector unit and said transfer control unit are responsive to the fourth address mode for adding the selected register contents and index value to obtain an adder unit output, and c. said address mode controller and said transfer control unit Are responsive to the fourth address mode for connecting said transfer unit to a second location defined by the adder unit output for conveying the information to or from the second location.
Claim 24
Dependent Claim
28 words
a transfer control unit responsive to said address mode controller and said register selector for enabling said transfer unit to transfer data to or from said selected register.
Claim 25
Dependent Claim
28 words
a transfer control unit responsive to said address mode controller and said register selector for enabling said transfer unit to transfer data to or from said selected register.
Claim 26
Dependent Claim
85 words
A data processing system as recited in claim 2 wherein the instruction address portion indicates first and second deferral states and wherein said address mode controller and said transfer control unit respond to the first deferral state for connecting said transfer unit to the selected location, said address mode controller and transfer control unit connecting said transfer unit to a second location defined by the selected location contents to convey the information to or from the second location in response to a second deferral state.
Claim 27
Dependent Claim
60 words
A data processing system as recited in claim 7 for responding to an instruction with a first address mode and second deferral state, said address mode controller and said transfer control unit being responsive to the instruction for connecting said transfer unit to the second location defined by the selected register contents to convey the information with the second location.
Claim 28
Dependent Claim
91 words
A data processing system as recited in claim 7 for responding to an instruction with a second address mode and second deferral state wherein: A. said address mode controller and said transfer control unit are responsive to the instruction for connecting said transfer unit to the second location defined by the contents of a third location addressed by the selected register contents to convey the information to or from the second location, and B. said transfer unit includes means responsive to said address mode controller for incrementing the selected register contents.
Claim 29
Dependent Claim
97 words
A data processing system as recited in claim 7 for responding to an instruction with a third address mode and a second deferral state wherein: A. said transfer unit includes means responsive to said address mode controller and said register selector for immediately decrementing the selected register contents, and B. said address mode controller and said transfer control unit are responsive to the instruction for connecting said transfer unit to the second location defined by the contents of a third location addressed by the decremented register contents for conveying the information to or from the second location.
Claim 30
Dependent Claim
129 words
A data processing system as recited in claim 7 for responding to an instruction with a fourth address mode and a second deferral state and a related index value wherein: A. said transfer unit includes an adder unit, B. said address mode controller, said register selector and said transfer control unit are responsive to the fourth address mode for adding the selected register contents and the index value to obtain an adder unit output, and C. said address mode controlled and said transfer control unit are responsive to the fourth address mode and second deferral state for connecting said transfer unit to the second location defined by the contents of a third location addressed by the adder unit output for conveying the information to or from the second location.
Claim 31
Dependent Claim
99 words
In a data processing system including a plurality of addressed locations and a processor unit for processing information stored at addressed locations in response to instructions with first and second address portions, said processor unit comprising: A. a plurality of addressed registers constituting additional addressed locations, each instruction address portion defining only one of said registers and one of said registers being a program counter for controlling the processor unit, B. a transfer unit coupled to the addressed locations for selectively conveying information to or from first and second of the addressed locations, and C. a control unit including:
Claim 32
Dependent Claim
99 words
In a data processing system including a plurality of addressed locations and a processor unit for processing information stored at addressed locations in response to instructions with first and second address portions, said processor unit comprising: A. a plurality of addressed registers constituting additional addressed locations, each instruction address portion defining only one of said registers and one of said registers being a program counter for controlling the processor unit, B. a transfer unit coupled to the addressed locations for selectively conveying information to or from first and second of the addressed locations, and C. a control unit including:
Claim 33
Dependent Claim
70 words
A data processing system as recited in claim 12 wherein each instruction address portion includes an address mode portion and a register address, said register selector being responsive to the first and second address signals for selecting said addressed registers in sequence and said control unit additionally comprising an address mode controller responsive to the address mode for modifying the utilization of the selected register contents by said processor unit.
Claim 34
Dependent Claim
60 words
A data processing system as recited in claim 13 for responding to a first address mode in one instruction address portion, said address mode controller and said transfer control unit being responsive to the first address mode and said timing unit for connecting said transfer unit to the selected register for conveying the information to or from said selected register.
Claim 35
Dependent Claim
84 words
A digital computer as recited in claim 13 for responding to a second address mode in one address portion of an instruction wherein: A. said address mode controller and said transfer control unit are responsive to the second address mode and said timing unit for connecting said transfer unit to an addressed location defined by the selected register contents for conveying the information contained therein, and B. said transfer unit includes means responsive to said address mode controller for incrementing the selected register contents.
Claim 36
Dependent Claim
39 words
A digital computer as recited in claim 15 wherein the one address portion identifies said program counter as said selected register, said control unit connecting said transfer unit to the addressed location following the instruction to convey the information.
Claim 37
Dependent Claim
96 words
A data processing system as recited in claim 13 for responding to a third address mode in one address portion of an instruction, wherein: A. said transfer unit includes means responsive to said address mode controller, said register selector and said timing unit for decrementing the selected register contents and B. said address mode controller and said transfer control unit are responsive to the third address mode and said timing unit for connecting said transfer unit to a second location defined by the decremented selected register contents for conveying information to ro from the second location.
Claim 38
Dependent Claim
123 words
A data processing system as recited in claim 13 for responding to a fourth address mode in one address portion of an instruction and a related index value wherein: A. said transfer unit includes an adder unit, B. said address mode controller, said register selector and said transfer control unit are responsive to the fourth address mode and said timing unit for adding the selected register contents and index value to obtain an adder unit output, and C. said address mode controller and said transfer control unit are responsive to the fourth address mode and said timing unit for connecting said transfer unit to a second location defined by the adder unit output for conveying the information to or from the second location.
Claim 39
Dependent Claim
50 words
A data processing system as recited in claim 18 wherein the one address portion identifies said program counter as said selected register, said control unit connecting said transfer unit to said program counter for adding the program counter contents and index value to obtain the address for the second location.
Claim 40
Dependent Claim
88 words
A data processing system as recited in claim 13 wherein each instruction address portion indicates first and second deferral states and wherein said address mode controller and said transfer control unit respond to said timing unit and the first deferral state for connecting said transfer unit to the selected location, said address mode controller and said transfer control unit connecting said transfer unit to a second location defined by the selected location contents to convey the information to or from the second location during the second deferral state.
Claim 41
Dependent Claim
87 words
A data processing system as recited in claim 20 wherein each address portion in an instruction comprises diverse address modes and register addresses, said transfer control unit being responsive to said address mode controller, said register selector, said timing unit and said instruction decoder for connecting said transfer unit to a first location defined by one address portion for conveying information to said processor unit and to another location as defined by the other address portion for transferring information from said processor unit to the second location.
Claim 42
Dependent Claim
43 words
A data processing system comprising A a plurality of addressed locations including a memory unit for storing operating instructions in sequence, certain instructions including at least one operand address consisting of address mode and register address portions, and B. a processor unit including:
Claim 43
Dependent Claim
43 words
A data processing system comprising A a plurality of addressed locations including a memory unit for storing operating instructions in sequence, certain instructions including at least one operand address consisting of address mode and register address portions, and B. a processor unit including:
Claim 44
Dependent Claim
46 words
A data processing system as recited in claim 22 wherein said address mode controller and said transfer control unit respond to second contents of the address mode portion for connecting said transfer unit to a second location addressed by the selected register contents for conveying data.
Claim 45
Dependent Claim
64 words
A data processing system as recited in claim 23 wherein said address mode controller and said transfer control unit respond to third contents of the address mode portion for connecting said transfer unit to the second location, the second location being addressed by the contents of a third location addressed by the selected register contents to convey data to or from the second location.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-18 | 1975-04-19 | 1975-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-18 | 1979-04-19 | 1979-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-18 | 1983-04-19 | 1983-10-19 | $7700.00 | Window Closed / Lapsed |