Patent US928701A successfully refreshed from Google Patents.
Patent US3614740A successfully refreshed from Google Patents.
US3614740A
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Data processing system with circuits for transferring between operating routines, interruption routines and subroutines
Assignee: Digital Equipment Corp
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Filing: 1970-03-23
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Granted: 1971-10-19
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Expires: 1990-03-23
Abstract
Abstract A data processing system processor unit for executing instructions from one of a plurality of partially completed operating routines. With each subroutine transfer a first register provides memory location address for storing a second register contents. The program count is stored in the second register; and the first subroutine instruction address is transferred to the program counter. A last subroutine instruction moves the second register contents to the program counter and the memory location contents to the second register. When an interruption routine is started, the contents of the program counter and a status register are transferred directly into a pair of memory locations defined by addresses from the first register. A last interruption routine instruction moves the contents of the two memory locations defined by addresses from the first register to the processor unit. The last operating routine to be started is always the first one to be completed so that any number of routines may be partially completed.
Inventors
- 👤 Bruce A Delagi
- 👤 Harold L Mcfarland Jr
- 👤 James F O'loughlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:35
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/461; G06F9/44; G06F9/448; G06F9/4482; G06F9/4484; G06F9/4486
Claims Analysis
Total Claims: 64
Claim 1
Independent Claim
154 words
A data processing system including a memory unit for storing related operating routine instructions as operating programs subroutines and interruption routines and a processor unit for processing instructions conveyed thereto in sequence from locations in said memory unit identified by a program counter, said processor unit additionally comprising: A. a succession of vacant locations in said memory unit, B. a register for providing addresses of the vacant locations in said memory unit, C. a control unit responsive to first and second transfer signals which identify memory locations for subroutines and interruption routines, respectively, said control unit modifying said program counter to identify an address for one of the subroutines and interruption routine instructions, and D. a transfer unit responsive to said register and said control unit for storing return information in said memory unit at a location identified by said register, the return information including said program counter contents for the preceding operating routine.
Claim 2
Dependent Claim
154 words
A data processing system including a memory unit for storing related operating routine instructions as operating programs subroutines and interruption routines and a processor unit for processing instructions conveyed thereto in sequence from locations in said memory unit identified by a program counter, said processor unit additionally comprising: A. a succession of vacant locations in said memory unit, B. a register for providing addresses of the vacant locations in said memory unit, C. a control unit responsive to first and second transfer signals which identify memory locations for subroutines and interruption routines, respectively, said control unit modifying said program counter to identify an address for one of the subroutines and interruption routine instructions, and D. a transfer unit responsive to said register and said control unit for storing return information in said memory unit at a location identified by said register, the return information including said program counter contents for the preceding operating routine.
Claim 3
Dependent Claim
62 words
A data processing system as recited in claim 1 wherein each subroutine and interruption routine includes a return instruction, said control unit additionally comprising means responsive to the return instruction for causing A. said transfer unit to transfer the return information to said processor unit from said memory, and B. said register to identify the next-occupied contiguous location in said memory unit.
Claim 4
Dependent Claim
9 words
said program counter contents to said second register, and
Claim 5
Dependent Claim
9 words
said program counter contents to said second register, and
Claim 6
Dependent Claim
50 words
the contents of the third memory block to said second register to thereby return processor unit execution to the instruction in the first memory block following the transfer instruction, and B. said register-modifying means causing said first register to identify a previously used contiguous address in the third memory block.
Claim 7
Dependent Claim
50 words
the contents of the third memory block to said second register to thereby return processor unit execution to the instruction in the first memory block following the transfer instruction, and B. said register-modifying means causing said first register to identify a previously used contiguous address in the third memory block.
Claim 8
Dependent Claim
48 words
the interruption address to said program counter for causing the processor unit to obtain the next instruction from the fourth memory block, and B. said register-modifying means causing said first register to identify a vacant contiguous address in the third memory block for storing said program counter contents.
Claim 9
Dependent Claim
48 words
the interruption address to said program counter for causing the processor unit to obtain the next instruction from the fourth memory block, and B. said register-modifying means causing said first register to identify a vacant contiguous address in the third memory block for storing said program counter contents.
Claim 10
Dependent Claim
13 words
a second register for identifying contiguous locations in a third memory block, and
Claim 11
Dependent Claim
13 words
a second register for identifying contiguous locations in a third memory block, and
Claim 12
Dependent Claim
9 words
a second register for defining third memory block locations,
Claim 13
Dependent Claim
9 words
a second register for defining third memory block locations,
Claim 14
Dependent Claim
54 words
transferring said third memory block location contents defined by said second register to said third register, and B. said modifying means being responsive to the return instruction for causing said second register to define the next contiguous occupied memory location whereby said processor unit obtains the next instruction from the first set of instructions.
Claim 15
Dependent Claim
54 words
transferring said third memory block location contents defined by said second register to said third register, and B. said modifying means being responsive to the return instruction for causing said second register to define the next contiguous occupied memory location whereby said processor unit obtains the next instruction from the first set of instructions.
Claim 16
Dependent Claim
22 words
means responsive to an interrupting signal for modifying said second register to identify the next vacant contiguous third memory block location, and
Claim 17
Dependent Claim
22 words
means responsive to an interrupting signal for modifying said second register to identify the next vacant contiguous third memory block location, and
Claim 18
Dependent Claim
3 words
a third register,
Claim 19
Dependent Claim
3 words
a third register,
Claim 20
Dependent Claim
54 words
an address in a second memory block identified by the transfer instruction to said program counter, said processor unit thereafter obtaining instructions from the second memory block, and D. means responsive to the transfer instruction for modifying said first register contents to identify a next vacant contiguous memory location in the third memory block.
Claim 21
Dependent Claim
54 words
an address in a second memory block identified by the transfer instruction to said program counter, said processor unit thereafter obtaining instructions from the second memory block, and D. means responsive to the transfer instruction for modifying said first register contents to identify a next vacant contiguous memory location in the third memory block.
Claim 22
Dependent Claim
78 words
A data processing system as recited in claim 2 wherein an operating routine instruction produces the first transfer signal and the last subroutine instruction is a subroutine return instruction, said processor unit additionally comprising a second register coupled to said transfer unit, signals being conveyed between said second register and the memory location identified by said first register and between said program counter and said second register in response to the operating routine instrucTion and subroutine return instruction.
Claim 23
Dependent Claim
87 words
A data processing system as recited in claim 3 wherein the return instruction for the second transfer signal is an interruption turn instruction and said processor unit additionally comprises a third register for storing processor unit operating information, said transfer unit and said first register being responsive to the second transfer signal and the interruption return instruction for conveying signals between said program counter and the memory location identified by said first register and between said third register and another memory location identified by said first register.
Claim 24
Dependent Claim
42 words
an arithmetic unit responsive to said program counter for sequentially executing instructions in the first memory block, one instruction being a transfer instruction with a subroutine address for a first instruction in the second memory block to cause execution of one subroutine,
Claim 25
Dependent Claim
42 words
an arithmetic unit responsive to said program counter for sequentially executing instructions in the first memory block, one instruction being a transfer instruction with a subroutine address for a first instruction in the second memory block to cause execution of one subroutine,
Claim 26
Dependent Claim
52 words
a transfer unit including means responsive to said interrupting signal generator for a. transferring said program counter contents to the location identified by said second register, and b. transferring the second memory block address to said program counter whereby said processor unIt obtains an interruption subroutine instruction from the second memory block.
Claim 27
Dependent Claim
52 words
a transfer unit including means responsive to said interrupting signal generator for a. transferring said program counter contents to the location identified by said second register, and b. transferring the second memory block address to said program counter whereby said processor unIt obtains an interruption subroutine instruction from the second memory block.
Claim 28
Dependent Claim
17 words
means for modifying said second register contents to define the next vacant contiguous third memory block location,
Claim 29
Dependent Claim
17 words
means for modifying said second register contents to define the next vacant contiguous third memory block location,
Claim 30
Dependent Claim
105 words
In a data processing system including a plurality of addressed memory locations for storing instructions and data in blocks of contiguous locations and a processor unit including a program counter for selecting instructions and data in a first memory block for conveyance to and processing in the processor unit and adapted to obtain instructions from a second memory block in response to a transfer instruction, said processor unit comprising: A. a first register for storing an address for a third memory block, B. a second register, C. a transfer unit coupled to said first and second registers and responsive to the transfer instruction for transferring
Claim 31
Dependent Claim
105 words
In a data processing system including a plurality of addressed memory locations for storing instructions and data in blocks of contiguous locations and a processor unit including a program counter for selecting instructions and data in a first memory block for conveyance to and processing in the processor unit and adapted to obtain instructions from a second memory block in response to a transfer instruction, said processor unit comprising: A. a first register for storing an address for a third memory block, B. a second register, C. a transfer unit coupled to said first and second registers and responsive to the transfer instruction for transferring
Claim 32
Dependent Claim
36 words
A data processing system as recited in claim 5 wherein the last instruction in the second memory block is a return instruction, A. said transfer unit additionally comprising means responsive to the return instruction for transferring
Claim 33
Dependent Claim
55 words
a transfer unit responsive to the transfer instruction for a. first transferring said third register contents to the location identified by said second register, b. secondly, transferring said program counter contents to said third register, and c. thirdly, transferring the subroutine address to said program counter whereby said arithmetic unit obtains the first subroutine instruction.
Claim 34
Dependent Claim
55 words
a transfer unit responsive to the transfer instruction for a. first transferring said third register contents to the location identified by said second register, b. secondly, transferring said program counter contents to said third register, and c. thirdly, transferring the subroutine address to said program counter whereby said arithmetic unit obtains the first subroutine instruction.
Claim 35
Dependent Claim
40 words
A data processing system as recited in claim 6 including means responsive to a peripheral unit for generating an interruption address in a fourth memory block, A. said transfer unit additionally comprising means responsive to the interruption address for transferring
Claim 36
Dependent Claim
79 words
A data processing system as recited in claim 7 wherein the last instruction in the fourth memory block is a second return instruction, A. said transfer unit additionally comprising means responsive to the second return instruction for transferring the last contents of the third memory block to said program counter so the processor unit obtains the next instruction and, B. said register-modifying means causing said first register to identify a previously used contiguous address in the third memory block.
Claim 37
Dependent Claim
93 words
A data processing system as recited in claim 7 wherein said processor unit includes a status word register and said peripheral-responsive Means also generates a status word address, A. said interruption-address-responsive means being responsive to the status word address for transferring said status word register contents to a location in the third memory block identified by said first register, and B. said register-modifying means causing said first register to sequentially define the next two vacant contiguous third memory block core locations for storing said status word register contents and said program counter contents.
Claim 38
Dependent Claim
90 words
A data processing system as recited in claim 9 wherein the last instruction in the fourth memory block is a return instruction, A. said transfer unit additionally comprising means responsive to the second return instruction for transferring the contents of the last two locations in the third memory block to said status register and said program counter, and B. said register-modifying means being responsive to the return instruction for causing said first register to identify a previously used address in the third memory block contiguous to the last two locations.
Claim 39
Dependent Claim
48 words
A data processing system comprising: A. a memory unit including a plurality of addressed locations for storing first and second sets of instructions in first and second blocks of contiguous memory locations respectively, said second instruction sets constituting subroutines, and B. a processor unit processing the instructions including
Claim 40
Dependent Claim
48 words
A data processing system comprising: A. a memory unit including a plurality of addressed locations for storing first and second sets of instructions in first and second blocks of contiguous memory locations respectively, said second instruction sets constituting subroutines, and B. a processor unit processing the instructions including
Claim 41
Dependent Claim
32 words
A data processing system as recited in claim 11 wherein the last subroutine instruction is a subroutine return instruction, additionally comprising: A. said transfer unit being responsive to the return instruction for
Claim 42
Dependent Claim
63 words
A data processing system as recited in claim 12 wherein said modifying means causes said second register contents to identify the next contiguous vacant locations in the third memory block prior to a transfer in response to a subroutine transfer instruction to identify the next contiguous occupied location in the third memory block after a transfer in response to a subroutine return instruction.
Claim 43
Dependent Claim
35 words
A data processing system as recited in claim 12 wherein said processor unit additionally comprises a temporary register for storing the subroutine address until said first and second transfers are completely by said transfer unit.
Claim 44
Dependent Claim
69 words
A data processing system as recited in claim 14 wherein the subroutine address is stored in a location identified by said program counter, said pRocessor unit additionally comprising means responsive to a subroutine address including said program counter for transferring the contents of a first location contiguous to the subroutine transfer instruction to said program counter and a second location contiguous to said first location to said third register.
Claim 45
Dependent Claim
63 words
A data processing system as recited in claim 14 wherein the subroutine transfer instruction designates the last contiguous location in the third memory block as containing a subroutine address and said program counter as said third register, said transfer means being responsive to the subroutine transfer instruction for exchanging the contents of the location identified by said second register and said program counter.
Claim 46
Dependent Claim
70 words
A data processing system as recited in claim 14 additionally comprising interrupting signal-generating means for generating an address in a fourth memory block and a status word and a status register in said processor unit for storing a status word, the fourth memory block containing an interruption subroutine and said processor unit additionally comprising: A. a decoder means responsive to said interrupting signal-generating means for causing said transfer unit to
Claim 47
Dependent Claim
89 words
A data processing system as recited in claim 17 wherein the last interruption subroutine instruction is an interruption return instruction, A. said processor unit additionally comprising means responsive to the interruption return instruction for transferring the contents of the last two locations in the third memory block to said status register and said program counter, and B. said modifying means being responsive to the interruption return instruction for causing said second register to identify a previously used address in the third memory block contiguous to the last two locations.
Claim 48
Dependent Claim
63 words
A data processing system as recited in claim 18 wherein said modifying means includes A. means for decrementing said second register contents before each transfer of said program counter contents and said status word register contents to the third memory block, and B. means for incrementing said second register contents after each transfer to said status word register and to said program counter.
Claim 49
Dependent Claim
63 words
A data processing system comprising: A. a memory unit including a plurality of addressed locations for storing first and second sets of instructions in first and second blocks of contiguous locations respectively, said second instruction sets constituting interruption routines, B. a generator for generating interrupting signals including an address in the second memory block, and C. a processor unit for processing instructions including
Claim 50
Dependent Claim
63 words
A data processing system comprising: A. a memory unit including a plurality of addressed locations for storing first and second sets of instructions in first and second blocks of contiguous locations respectively, said second instruction sets constituting interruption routines, B. a generator for generating interrupting signals including an address in the second memory block, and C. a processor unit for processing instructions including
Claim 51
Dependent Claim
70 words
A data processing system as recited in claim 20 wherein the last interruption routine instruction is an interruption return instruction. A. said transfer unit including means for transferring the program counter contents in the third memory block to said program counter, and B. said modifying means being responsive to the interruption return instruction for causing said second register to identify the next occupied contiguous location in the third memory block.
Claim 52
Dependent Claim
91 words
A data processing system as recited in claim 20 additionally including a status word register, A. said interrupting signal generator additionally generating an address for a status word, B. said transfer unit including means for transferring said status word register contents to a vacant location in the third memory block, and C. said modifying means being responsive to said interrupting signal generator for causing said second register to identify the next two contiguous vacant locations in the third memory block for storing said status word register and said program counter contents.
Claim 53
Dependent Claim
92 words
A data processing system as recited in claim 22 wherein the last instruction in an interruption routine is an interruption return instruction, A. said transfer unit including means responsive to the return instruction for transferring the status word in the third memory block to the status word register and the program counter contents stored in the other third memory block location to said program counter, and B. said modifying means being responsive to the interruption routine instruction for causing said register to identify the next-occupied contiguous location in the third memory block.
Claim 54
Dependent Claim
41 words
A data processing system as recited in claim 23 wherein said modifying means comprises: A. means responsive to said interrupting signal generator for decrementing said second register, and B. means for incrementing said second register in response to a return instruction.
Claim 55
Independent Claim
119 words
A method for causing a processor unit in a data processing system which is obtaining instructions from a first block of memory unit locations to obtain instructions from another block of locations wherein the processor unit includes a program counter for identifying instructions to be obtained, one instruction being a transfer instruction identifying a first register and a second memory block location, and a second register for identifying third memory block locations, said method comprising the steps of: A. transferring the first register contents to the next vacant third memory block location identified by the second register, B. transferring the program counter contents to the first register, and C. transferring the second memory block address to the program counter.
Claim 56
Independent Claim
119 words
A method for causing a processor unit in a data processing system which is obtaining instructions from a first block of memory unit locations to obtain instructions from another block of locations wherein the processor unit includes a program counter for identifying instructions to be obtained, one instruction being a transfer instruction identifying a first register and a second memory block location, and a second register for identifying third memory block locations, said method comprising the steps of: A. transferring the first register contents to the next vacant third memory block location identified by the second register, B. transferring the program counter contents to the first register, and C. transferring the second memory block address to the program counter.
Claim 57
Dependent Claim
54 words
A method as recited in claim 25 wherein the last location in the memory block contains a return instruction, said method being responsive to the return instruction by A. transferring the first register contents to the program counter, and B. transferring the contents of the next-occupied third memory block location to the first register.
Claim 58
Dependent Claim
46 words
A method as recited in claim 26 additionally comprising the step of modifying the second register contents in response to the transfer and return instructions for identifying the address of the last-occupied third memory block location to control transfers to and from the third memory block.
Claim 59
Dependent Claim
47 words
A method as recited in claim 27 wherein said modifying of the second register contents includes: A. decrementing the second register before said transfer steps in response to the transfer instruction, and B. incrementing said second register after said transfer steps in response to the return instruction.
Claim 60
Dependent Claim
64 words
A method as recited in claim 28 wherein the processor unit includes a temporary register, said second memory block address transfer steP including: A. transferring the address of the second memory block location to the temporary register before said transfer step from the first register, and B. transferring the temporary register contents to the program counter after said transfer step from the program counter.
Claim 61
Dependent Claim
74 words
A method as recited in claim 29 wherein the transfer instruction, second memory block address and additional information are stored in contiguous locations in the first memory block, and the transfer instruction identifies the program counter to obtain the second memory address, said transfer step to the first register storing the information from the first memory block and said transfer step to said program counter storing the address for the second set of instructions.
Claim 62
Dependent Claim
69 words
A method as recited in claim 29 wherein the transfer instruction identifies the program counter as the first register and the contents of a location identified by the second register as a memory address, said transfer steps to the temporary register, from the first register and from the program counter causing the contents of the location identified by the second register and the program counter contents to be exchanged.
Claim 63
Dependent Claim
104 words
A method as recited in claim 29 wherein the processing system additionally comprises means for generating a plurality of interrupting signals each identifying an address in a fourth memory block, the fourth memory block containing an address for an interruption routine and a status word for storage in a status word register, said method responding to an interrupting signal by: A. decrementing the second register, B. transferring the program counter contents to the third memory block location identified by the second register, C. decrementing the second register, D. transferring the status register contents to the third memory block location identified by the second register.
Claim 64
Dependent Claim
76 words
A method as recited in claim 32 wherein each interruption routine terminates with an interrupt return instruction, said method responding to the return instruction by A. transferring the status word in the third memory block location identified by the second register to the status word register, B. incrementing the second register, C. transferring the contents of the third memory block location identified by the second register to the program counter, and D. incrementing the second register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-18 | 1975-04-19 | 1975-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-18 | 1979-04-19 | 1979-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-18 | 1983-04-19 | 1983-10-19 | $7700.00 | Window Closed / Lapsed |