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US3611307A Expired / Lapsed US ⏱️ 0.0 years remaining

Execution unit shared by plurality of arrays of virtual processors

Assignee: International Business Machines Corp
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Filing: 1969-04-03
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Granted: 1971-10-05
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Expires: 1989-04-03
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Abstract

Abstract A multiplicity of arrays of digital machines, said machines time sharing a single execution unit having multiple execution facilities is disclosed. A digital machine is termed a virtual processor and can be defined as a basic digital computer, absent an execution unit, secondary control and storage unit. The arrays of virtual processors time share a common execution unit. Selection means associated with each array sequentially sample each virtual processor in its given time slot. If a given virtual processor requests service during its time slot, its request becomes a candidate for presentation to the execution unit. Since there are a multiplicity of arrays, there may be a multiplicity of service requests during a given time slot. A priority controller determines priority among the arrays such that the highest priority array having a currently sampled virtual processor requesting service will gate its service request and associated operands to the execution unit. Means are provided for gating the results of the requested service back to the requesting virtual processor.

Inventors

  • 👤 Albert Podvin
  • 👤 Michael J Flynn

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-22 23:38
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3867; G06F9/3875; G06F9/44; G06F9/455; G06F9/45533; G06F9/46; G06F9/48; G06F9/4806; G06F9/4843; G06F9/4881

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 44 words
In a multiPle operand stream computer system, the combination of: an execution unit; a plurality of arrays each containing a plurality of virtual processors and cyclically operative priority means for enabling each of said virtual processors in said arrays to time-share said execution unit.
Claim 2
Dependent Claim 44 words
In a multiPle operand stream computer system, the combination of: an execution unit; a plurality of arrays each containing a plurality of virtual processors and cyclically operative priority means for enabling each of said virtual processors in said arrays to time-share said execution unit.
Claim 3
Dependent Claim 13 words
The combination of claim 1 wherein said cyclically operative execution unit it pipelined.
Claim 4
Dependent Claim 37 words
The combination of claim 1 wherein said priority means includes: first control means for periodically rotating priority among said arrays, and second control means for disabling said first control means and transferring priority to a designated array.
Claim 5
Dependent Claim 57 words
The combination of claim 2 wherein said pipelined execution unit includes: a plurality of staged execution facilities disposed to receive operand information from said arrays, means associated with said facilities for indicating to a requesting virtual processor that its request has been accepted; and means for transmitting the results of execution back to said requesting virtual processor.
Claim 6
Dependent Claim 79 words
The combination of claim 4 wherein a first group of execution facilities executes operands at a first speed and at least one other execution facility executes operands at a speed slower than said first speed, said at least one other execution facility including means responsive to the acceptance of a request from a requesting processor for inhibiting the availability of a new request in said requesting processor until said accepting facility has substantially completed execution of said accepted request.
Claim 7
Dependent Claim 52 words
In a multiple operand stream computer system, the combination of: an execution unit; a plurality of arrays of virtual processors, each array having means for presenting a service request during given time periods; and priority means for selecting a service request from one of said arrays for presentation to said execution unit.
Claim 8
Dependent Claim 52 words
In a multiple operand stream computer system, the combination of: an execution unit; a plurality of arrays of virtual processors, each array having means for presenting a service request during given time periods; and priority means for selecting a service request from one of said arrays for presentation to said execution unit.
Claim 9
Dependent Claim 80 words
The combination of claim 6 wherein each array includes: a group of virtual processors each receiving operands from a storage system and having the capability of periodically making operands available for execution; service request means within each virtual processor for providing an indication that operands are available for execution; a sampling means for periodically sampling each service request means; and gating means responsive to the sampling of an active service request means for gating said indication to said priority means.
Claim 10
Dependent Claim 22 words
The combination of claim 7 further including means for gating said selected service request and its associated operands to said execution unit.
Claim 11
Dependent Claim 39 words
The combination of claim 6 wherein said cyclically operative priority means includes: cyclically operative means for rotating priority among said arrays; and logic and storage means for overriding said cyclically operative means to transfer priority to a specified array.
Claim 12
Dependent Claim 223 words
In a multiple operand stream computer system, the combination of: a pipelined execution unit; a plurality of arrays of virtual processors, each of said arrays capable of having associated therewith up to N virtual processors; busing means associated with each of said arrays for transmitting operands and results from said virtual processors to said execution unit; means associated with each array for indicating a service request to said execution unit; ring counter means associated with each array for indicating a particular processor within said array as a candidate to transmit said indicated request and its operands to said execution unit during a given time period; a priority ring counter associated with gating means for establishing array priority during said given time period, said selection means selecting the highest priority array having a service request outstanding during a given time period; a first register means for indicating a particular array as having priority regardless of the priority established by said priority ring couNter; logic means responsive to signals from said priority ring counter, said service request indicating means and said first register means, said logic means generating signals to override said established priority and transfer priority to said particular array; and gating means for transmitting the results of said requested service back to said particular processor which was associated with the array having priority.
Claim 13
Dependent Claim 223 words
In a multiple operand stream computer system, the combination of: a pipelined execution unit; a plurality of arrays of virtual processors, each of said arrays capable of having associated therewith up to N virtual processors; busing means associated with each of said arrays for transmitting operands and results from said virtual processors to said execution unit; means associated with each array for indicating a service request to said execution unit; ring counter means associated with each array for indicating a particular processor within said array as a candidate to transmit said indicated request and its operands to said execution unit during a given time period; a priority ring counter associated with gating means for establishing array priority during said given time period, said selection means selecting the highest priority array having a service request outstanding during a given time period; a first register means for indicating a particular array as having priority regardless of the priority established by said priority ring couNter; logic means responsive to signals from said priority ring counter, said service request indicating means and said first register means, said logic means generating signals to override said established priority and transfer priority to said particular array; and gating means for transmitting the results of said requested service back to said particular processor which was associated with the array having priority.

References Cited (Backward Citations)

US3317898A Cited
US3346851A Cited
US3312954A Cited
US3421150A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-10-04 1975-04-05 1975-10-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-10-04 1979-04-05 1979-10-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-10-04 1983-04-05 1983-10-05 $7700.00 Window Closed / Lapsed

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