High speed data transmission system utilizing nonbinary correlative techniques

Claim 2

In a digital communication system including a transmitter wherein a binary input signal in serial form is converted into a nonbinary correlative signal the amplitude of successive digit intervals of which may be one of an uppermost level, a lowermost level, or one of a plurality of levels intermediate said uppermost and lowermost levels, for transmission to a receiver over a medium in which errors may be introduced in transmission, apparatus at said receiver for detecting said errors, comprising: means for deriving from the received nonbinary correlative signal a replica of said binary input signal in parallel form except for such errors that may have occurred in transmission; means operative on said replica of said binary signal for simulating said nonbinary correlative signal except for such errors that may have occurred in transmission; means for determining during each digit interval of the received signal the presence or absence of said uppermost or lowermost amplitude levels; means for determining whether said simulated signal has an uppermost or a lowermost amplitude level during digit intervals when said received signal is of uppermost or lowermost amplitude, respectively; and means for producing an error indication in response to a lack of coincidence of uppermost or lowermost levels between said received signal and said simulated signal during corresponding bit intervals.

Claim 3

Apparatus in accordance with claim 1, wherein said means for simulating said nonbinary correlative signal includes: a coder connected to the output of said replica deriving means and operative to introduce memory into said replica and to produce at its output a plurality of separately coded parallel binary output signals; and a digital logic correlator connected to the output of said coder and operative to introduce correlation into said coded binary signals and to produce at its output said simulated nonbinary correlative signal.

Claim 4

In a digital communication system having a band-limited transmission channel, apparatus for converting a serial binary data stream into a nonbinary correlative signal at the transmitter and recovering the serial binary data at the receiver, which comprises at the transmitter: a serial-to-parallel converter operative to convert said serial binary data stream into log2Q parallel data streams where Q 2n and n is an integer greater than two; a coder having an input connected to the output of said converter and an output, said coder being operative separately to introduce memory into each of said log2Q parallel binary data streams and to produce at its output a like plurality of coded parallel binary data streams; means connected to the output of said coder for combining said separately coded parallel binary data streams by modulo Q addition to produce a coded nonbinary data stream having Q amplitude levels; subtracting means having an input connected to the output of said combining means and an output, said subtracting means being operative to subtract the second digit back from the present digit of said Q-level signal to produce a level coded nonbinary correlative signal having (2Q-1) amplitude levels for transmission to a receiver and which comprises at said receiver; means for determining which one of said (2Q-1) received levels exists during each successive digit interval of said reCeived nonbinary correlative signal; (2Q-1) AND-gates one for each signal amplitude, namely a first AND-gate operatively connected to receive only the lowermost amplitude level output of said determining means, said first AND-gate having an output only when its input is below a predetermined threshold; a second AND-gate operatively connected to receive only the uppermost amplitude level output of said determining means, said second AND-gate having an output only when its input is below a predetermined threshold; 2Q-3 intermediate two-input AND-gates each having an inhibit input, said intermediate AND-gates, respectively, operatively connected to adjacent outputs of the determining means with said inhibit input being connected to the upper of the adjacent amplitude levels; a shift register containing log2Q stages with each stage having a set and reset input; and, 2log2Q OR-gates connected in pairs one of each pair having an output connected to said set input and the other OR-gate of the pair being connected to the reset input of said shift register, the OR-gate inputs being operatively connected to the AND-gate outputs so that only one OR-gate of each said pair will have an output for each input signal amplitude and thereby converting the nonbinary signal amplitude into a serial binary data stream.

Claim 5

In a digital communication system having a band-limited transmission channel, apparatus for converting a serial binary data stream into a nonbinary correlative signal at the transmitter and recovering the serial binary data at the receiver, which comprises at the transmitter: a serial-to-parallel converter operative to convert said serial binary data stream into log2Q parallel data streams where Q 2n and n is an integer greater than two; a coder having an input connected to the output of said converter and an output, said coder being operative separately to introduce memory into each of said log2Q parallel binary data streams and to produce at its output a like plurality of coded parallel binary data streams; means connected to the output of said coder for combining said separately coded parallel binary data streams by modulo Q addition to produce a coded nonbinary data stream having Q amplitude levels; subtracting means having an input connected to the output of said combining means and an output, said subtracting means being operative to subtract the second digit back from the present digit of said Q-level signal to produce a level coded nonbinary correlative signal having (2Q-1) amplitude levels for transmission to a receiver and which comprises at said receiver; means for determining which one of said (2Q-1) received levels exists during each successive digit interval of said reCeived nonbinary correlative signal; (2Q-1) AND-gates one for each signal amplitude, namely a first AND-gate operatively connected to receive only the lowermost amplitude level output of said determining means, said first AND-gate having an output only when its input is below a predetermined threshold; a second AND-gate operatively connected to receive only the uppermost amplitude level output of said determining means, said second AND-gate having an output only when its input is below a predetermined threshold; 2Q-3 intermediate two-input AND-gates each having an inhibit input, said intermediate AND-gates, respectively, operatively connected to adjacent outputs of the determining means with said inhibit input being connected to the upper of the adjacent amplitude levels; a shift register containing log2Q stages with each stage having a set and reset input; and, 2log2Q OR-gates connected in pairs one of each pair having an output connected to said set input and the other OR-gate of the pair being connected to the reset input of said shift register, the OR-gate inputs being operatively connected to the AND-gate outputs so that only one OR-gate of each said pair will have an output for each input signal amplitude and thereby converting the nonbinary signal amplitude into a serial binary data stream.

Claim 6

Apparatus for generating a correlative nonbinary signal having (2Q-1) signal amplitudes; where Q 4, and the nonbinary signal is generated according to the relation C B+ Delta 2C Mod Q, where B is the noncorrelated digital input signal, C is the coded output signal, Delta 2 is a delay of two digit intervals of C, and Q is equal to the number of nonbinary signal levels of B; from a noncorrelated serial binary signal, which comprises: means for converting the noncorrelated serial binary signal into two parallel binary streams represented by X and Y; means for coding each of said parallel binary streams according to the relation c1 XZ''W'' YZ''W+X''ZW+Y''ZW'' C2 ZXW''+Y''ZW+X''Z''W+YZ''W'''' WHERE, C1 is the coded output representation of the binary stream x, c2 is the coded output representation of the binary stream y, z is c1 delayed by two digit intervals Delta 2c1, w is c2 delayed by two digit intervals Delta 2c2 and, the prime denotes negation; means for combining the two coded binary streams into a nonbinary digital signal having Q levels; and, means for subtracting the second digit back from the present digit of the nonbinary digital signal to introduce correlation and level conversion, thereby to obtain a nonbinary correlative output signal having (2Q-1) amplitude levels.

Claim 7

Apparatus for generating a correlative nonbinary signal having (2Q-1) signal amplitudes; where Q 4, and the nonbinary signal is generated according to the relation C B+ Delta 2C Mod Q, where B is the noncorrelated digital input signal, C is the coded output signal, Delta 2 is a delay of two digit intervals of C, and Q is equal to the number of nonbinary signal levels of B; from a noncorrelated serial binary signal, which comprises: means for converting the noncorrelated serial binary signal into two parallel binary streams represented by X and Y; means for coding each of said parallel binary streams according to the relation c1 XZ''W'' YZ''W+X''ZW+Y''ZW'' C2 ZXW''+Y''ZW+X''Z''W+YZ''W'''' WHERE, C1 is the coded output representation of the binary stream x, c2 is the coded output representation of the binary stream y, z is c1 delayed by two digit intervals Delta 2c1, w is c2 delayed by two digit intervals Delta 2c2 and, the prime denotes negation; means for combining the two coded binary streams into a nonbinary digital signal having Q levels; and, means for subtracting the second digit back from the present digit of the nonbinary digital signal to introduce correlation and level conversion, thereby to obtain a nonbinary correlative output signal having (2Q-1) amplitude levels.

Claim 8

Apparatus according to claim 4 wherein said coding means comprises: a first set of four three-input AND-gates having X, Y, Z and W inputs to the set; a first OR-gate having four inputs and an output, one said input being connected to the output of one of the four three-input AND-gates of said first set; a second set of four three-input AND-gates having X, Y, Z and W inputs to the set; a second OR-gate having four inputs and an output, one said input being connected to the output of one of the four three-input AND-gates of the second set; a first delay circuit with a delay of substantially two digit intervals, Delta 2, having an input and a delayed output the input being connected to the output of said first OR-gate, said delayed output being connected both to an input of said first AND-gate set and to an input of said second AND-gate set; a second delay circuit with a delay of substantially two digit intervals, Delta 2, having an input and a delayed output, the input being connected to the output of said second OR-gate, and said delayed output being connected both to an input of said first AND-gate set and to an input of said second AND-gate set; said first OR-gate having one output state for any one of the following input conditions to the first AND-gate set: X Z'' W'' X''Z W X'' Z W Y Z'' W Y'' Z W'' where the prime indicates negation, and the other state for all other conditions; and said second OR-gate having one output state for any one of the following input conditions to the second AND-gate set: X Z W'' X Z'' W Y Z W'' Y Z'' W and the other state for all other input conditions.

Claim 9

Apparatus according to claim 5 wherein said subtracting means further comprises: a band-pass filter in which the frequency-attenuation characteristic substantially approximates the mathematical expression 1-e j2 t over the interval f 0 to f 1/2 T Hz., where T is the digit interval of the nonbinary correlative signal, omega is equal to 2 pi times the frequency, e is the Naperian base of the natural logarithm, and j is the standard operator notation for the square root of -1.

Claim 10

Apparatus according to claim 6 wherein said converting means further comprises a two-stage shift register.