Dc-to-dc converter

Claim 1

A DC-to-DC converter comprising an input circuit adapted for connection to a source of direct-current; an output circuit adapted to deliver DC to a load and including a linear transformer having a primary winding and a secondary winding, control circuit means operative from source current to generate timed and shaped control pulses the amplitudes of which are substantially constant and the duration of which are conformed in inverse magnitude to the instantaneous voltage of the source; switching means actuated by said control pulses to apply source current in successive power pulses to said primary winding whereby the latter is energized by pulses of source current which have a substantially constant energy content; means in said output circuit operative to rectify and integrate power pulses derived from said secondary winding to provide a unidirectional and substantially steady state current for utilization by a load, said transformer primary winding being split into two sections and said switching means being actuated in power cycles by gating pulses applied thereat in each power cycle, and said control circuit means includes an oscillator providing two timing pulses per cycle of oscillation, together with multivibrator means triggered under control of both timing pulses in each oscillator cycle to produce angularly spaced gating pulses in pairs in each power cycle with the spacing between the successive gating pulses in each pair being changed in inverse proportion to each change of source voltage at any given instant from said normal value thereof, said switching means being operative under control of each pair of gating pulses in each power cycle to switch a power pulse of source current into a different one of said primary sections, multiple arrays, each comprising a plurality of transistors having base, emitter and collector electrodes; said multiple arrays comprising a group operatively associated with each transformer primary section, and the several arrays comprising each said group being connected in parallel and with the bases of the first transistor in each array of the group being connected to define a joint input base terminal, driving circuits, said joint input base terminal connecting with a corresponding driving circuit, and the respective common collector terminals connected to define a joint coLlector terminal; and the emitter electrodes of the last transistors in each array being connected to define a joint emitter terminal, and the said joint collector and emitter terminals being connected to source current through the appertaining primary section.