Programmable digital differential analyzer integrator

Claim 2

A programmable digital differential analyzer integrator comprising means including first register means for registering first digital signals representative of variations in a dependent quantity of a mathematical function, multiplying means coupled to said means including first register means and adapted to receive second digital signals representative of variations in an independent quantity of a mathematical function for providing third digital signals representative of the product of the value currently registered in said first register means and said second digital signals, means including second register means coupled to said multiplying means for forming output signals upon the occurrence of a predetermined value in said second register means, said multiplying means being adapted to register said third digital signals in said second register means upon each occurrence of said second digital signal, programmable interconnecting means for selectively rendering said first and second register means and said multiplying means responsive to said signal representations, said programmable interconnecting means including storage, decoding and gating circuit means coupled to said first and second register means and said multiplying means for selectively changing the effective interconnections of said integrator by changing the information temporarily programmed therein, and in which all of said means are disposed on a common substrate.

Claim 3

A programmable digital differential analyzer integrator comprising means including first register means for registering first digital signals representative of variations in a dependent quantity of a mathematical function, multiplying means coupled to said means including first register means and adapted to receive second digital signals representative of variations in an independent quantity of a mathematical function for providing third digital signals representative of the product of the value currently registered in said first register means and said second digital signals, means including second register means coupled to said multiplying means for forming output signals upon the occurrence of a predetermined value in said second register means, said multiplying means being adapted to register said third digital signals in second register means upon each occurrence of said second digital signal, programmable interconnecting means for selectively rendering said first and second register means and said multiplying means responsive to said signal representations, said programmable interconnecting means including storage, decoding and gating circuit means coupled to said first and second register means and said multiplying means for selectively changing the effective interconnections of said integrator by changing the information temporarily programmed therein, and in which all of said means form a single monolithic semiconductor circuit.

Claim 4

A programmable digital differential analyzer integrator comprising means including first register means for registering first digital signals representative of variations in a dependent quantity of a mathematical function, multiplying means coupled to said means including first register means and adapted to receive second digital signals representative of variations in an independent quantity of a mathematical function for providing third digital signals representative of the product of the value currently registered in said first register means and said second digital signals, means including second register means coupled to said multiplying means for forming output signals upon the occurrence of a predetermined value in said second register means, said multiplying means being adapted to register said third digital signals in second register means upon each occurrence of said second digital signal, programmable interconnecting means for selectively rendering said first and second register means and said multiplying means responsive to said signal representations, said programmable interconnecting means including storage, decoding and gating circuit means coupled to said first and second register means and said multiplying means for selectively changing the effective interconnections of said integrator by changing the information temporarily programmed therein, and in which all of said means form a single monolithic semiconductor circuit.

Claim 5

A programmable digital differential analyzer integrator comprising means including first register means for registering first digital signals representative of variations in a dependent quantity of a mathematical function, multiplying means coupled to said means including first register means and adapted to receive second digital signals representative of variations in an independent quantity of a mathematical function for providing third digital signals representative of the product of the value currently registered in said first register means and said second digital signals, means including second register means coupled to said multiplying means for forming output signals upon the occurrence of a predetermined value in said second register means, said multiplying means being adapted to register said third digital signals in said second register means upon each occurrence of said second digital signal, programmable interconnecting means for selectively rendering said first and second register means and said multiplying means responsive to said signal representations, said means including first register means including Y-register means for registering digital signal iNdications representative of said dependent quantity, dY-counter-register means for registering incremental variations of said dependent quantity, adding means coupled to receive said dependent quantity signal indications and said incremental variations thereof for providing said first digital signals representative of the sum thereof and for introducing said first digital signals into said Y-register means, said integrator further including gating means coupled between said dY-counter means and said adding means and responsive to a start signal for effecting said summation, and said programmable interconnecting means including a common input-output line adapted to be interconnected with other integrators, a common initiation line adapted to receive initiation signals, gating means coupled to said common lines, information storage means for storing initiation information coupled to at least a portion of said gating means and decoding means adapted to be responsive to address signals for selectively gating portions of said gating means for selectively rendering said signals effective.

Claim 6

A programmable digital differential analyzer integrator comprising means including first register means for registering first digital signals representative of variations in a dependent quantity of a mathematical function, multiplying means coupled to said means including first register means and adapted to receive second digital signals representative of variations in an independent quantity of a mathematical function for providing third digital signals representative of the product of the value currently registered in said first register means and said second digital signals, means including second register means coupled to said multiplying means for forming output signals upon the occurrence of a predetermined value in said second register means, said multiplying means being adapted to register said third digital signals in said second register means upon each occurrence of said second digital signal, programmable interconnecting means for selectively rendering said first and second register means and said multiplying means responsive to said signal representations, said means including first register means including Y-register means for registering digital signal iNdications representative of said dependent quantity, dY-counter-register means for registering incremental variations of said dependent quantity, adding means coupled to receive said dependent quantity signal indications and said incremental variations thereof for providing said first digital signals representative of the sum thereof and for introducing said first digital signals into said Y-register means, said integrator further including gating means coupled between said dY-counter means and said adding means and responsive to a start signal for effecting said summation, and said programmable interconnecting means including a common input-output line adapted to be interconnected with other integrators, a common initiation line adapted to receive initiation signals, gating means coupled to said common lines, information storage means for storing initiation information coupled to at least a portion of said gating means and decoding means adapted to be responsive to address signals for selectively gating portions of said gating means for selectively rendering said signals effective.

Claim 7

A digital differential analyzer comprising a plurality of interconnected programmable digital differential analyzer integrators wherein each of said integrators includes means including first register means for registering first digital signals representative of variations in a dependent quantity of a mathematical function, multiplying means coupled to said means including first register means and adapted to receive second digital signals representative of variations in an independent quantity of a mathematical function for providing third digital signals representative of the product of the value currently registered in said first register means and said second digital signals, means including second register means coupled to said multiplying means for forming output signals upon the occurrence of a predetermined value in said second register means, said multiplying means being adapted to register said third digital signals in said second register means upon each occurrence of said second digital signals, common data bus means coupled to each of said integrators and responsive to data inputs and said output signals, gating means coupled between said common bus means and each of said integrators for selectively rendering said data inputs and outputs effective, and storage means coupled to at least a portion of said gating means for selectively actuating certain of said gating means as a function of stored information whereby interconnection between certain integrators is rendered effective.

Claim 8

A digital differential analyzer comprising a plurality of interconnected programmable digital differential analyzer integrators wherein each of said integrators includes means including first register means for registering first digital signals representative of variations in a dependent quantity of a mathematical function, multiplying means coupled to said means including first register means and adapted to receive second digital signals representative of variations in an independent quantity of a mathematical function for providing third digital signals representative of the product of the value currently registered in said first register means and said second digital signals, means including second register means coupled to said multiplying means for forming output signals upon the occurrence of a predetermined value in said second register means, said multiplying means being adapted to register said third digital signals in said second register means upon each occurrence of said second digital signals, common data bus means coupled to each of said integrators and responsive to data inputs and said output signals, gating means coupled between said common bus means and each of said integrators for selectively rendering said data inputs and outputs effective, and storage means coupled to at least a portion of said gating means for selectively actuating certain of said gating means as a function of stored information whereby interconnection between certain integrators is rendered effective.

Claim 9

A digital differential analyzer of the character recited in claim 4 and further including initial condition bus means adapted to receive initial condition signals representative of values to which certain of said register means and storage means are initially set and interconnection signals, loading gate means coupled between said initial condition bus means and said certain of said register means and storage means for selectively loading said certain register and storage means, and initialization decoding means adapted to receive externally generated selection signals and coupled to said loading gate means for selectively actuating at least a portion of said loading gate means.

Claim 10

A programmable digital differential analyzer comprising a plurality of digital differential analyzer integrator means each having an input and an output, common data bus means coupled to all said inputs and outputs, a plurality of first gating means coupled between said data bus means and the plurality of inputs, respectively, for selectively transmitting data signals from said data bus means to said inputs, a plurality of second gating means coupled between said data bus means and the plurality of outputs, respectively, for selectively transmitting data signals from said outputs to said data bus means, and programmable means coupled to said gating means for selectively rendering said gating means conductive.

Claim 11

A programmable digital differential analyzer comprising a plurality of digital differential analyzer integrator means each having an input and an output, common data bus means coupled to all said inputs and outputs, a plurality of first gating means coupled between said data bus means and the plurality of inputs, respectively, for selectively transmitting data signals from said data bus means to said inputs, a plurality of second gating means coupled between said data bus means and the plurality of outputs, respectively, for selectively transmitting data signals from said outputs to said data bus means, and programmable means coupled to said gating means for selectively rendering said gating means conductive.

Claim 12

A programmable digital differential analyzer of the character recited in claim 6 in which all of said means are disposed on a common substrate.

Claim 13

A programmable digital differential analyzer of the character recited in claim 6 in which all of said means form a single monolithic semiconductor circuit.

Claim 14

A programmable digital differential analyzer of the character recited in claim 6 further including a plurality of first storage means coupled between said first gating means and said inputs, respectively, for storing the data signals selectively transmitted from said data bus means through said first gating means.

Claim 15

A programmable digital differential analyzer of the character recited in claim 9 in which said plurality of second gating means are coupled to receive sequentially occuring gating signals, respectively, to sequentially render said second gating means conductive thereby sequentially transmitting data signals from said outputs of said respective integrators to said data bus means.

Claim 16

A programmable digital differential analyzer of the character recited in claim 10 in which said programmable means comprises a plurality of timing means coupled to said plurality of first gating means, respectively, for providing predetermined timing signals concurrently with said gating signals for selectively rendering said plurality of first gating means conductive, thereby effecting predetermined interconnections among said outputs and said inputs in accordance with said predetermined timing signals.

Claim 17

A programmable digital differential analyzer of the character recited in claim 11 in which each said timing means comprises shift register means for sequentially providing signals representative of the bits of a predetermined digital number stored therein, thereby providing said timing signals.

Claim 18

A programmable digital differential analyzer of the character recited in claim 12 in which said programmable means further includes means for changing said stored digital numbers thereby changing the effective interconnections among said integrators.

Claim 19

A programmable digital differential analyzer comprising a plurality of digital differential analyzer integrator means each having a dX-input and a dZ-output certain of said integrator means having a dY-input, common data bus means coupled to all said dX and dY-inputs and all said dZ-outputs, a plurality of first gating means coupled between said data bus means and the plurality of dX-inputs, respectively, for selectively transmitting data signals from said data bus means to said dX-inputs, a plurality of second gating means coupled between said data bus means and the plurality of dZ-inputs, respectively, for selectively transmitting data signals from said dZ-outputs to said data bus means, third gating means coupled between said data bus means and the dY-inputs, respectively, for selectively transmitting signals from said data bus means to said dY-inputs, and programmable means coupled to said gating means for selectively rendering said gating means conductive.

Claim 20

A programmable digital differential analyzer comprising a plurality of digital differential analyzer integrator means each having a dX-input and a dZ-output certain of said integrator means having a dY-input, common data bus means coupled to all said dX and dY-inputs and all said dZ-outputs, a plurality of first gating means coupled between said data bus means and the plurality of dX-inputs, respectively, for selectively transmitting data signals from said data bus means to said dX-inputs, a plurality of second gating means coupled between said data bus means and the plurality of dZ-inputs, respectively, for selectively transmitting data signals from said dZ-outputs to said data bus means, third gating means coupled between said data bus means and the dY-inputs, respectively, for selectively transmitting signals from said data bus means to said dY-inputs, and programmable means coupled to said gating means for selectively rendering said gating means conductive.

Claim 21

A programmable digital differential analyzer of the character recited in claim 14 further including a plurality of first storage means coupled between said first gating means and said dX-inputs, respectively, for storing the data signals selectively transmitted from said data bus means through said gating means, and second storage means coupled between said third gating means and said dY-inputs, respectively, for storing the data signals transmitted from said data bus means through said third gating means.

Claim 22

A programmable digital differential analyzer of the character recited in claim 15 in which said second storage means include means for accumulating said data signals transmiTted through said third gating means.

Claim 23

A programmable digital differential analyzer of the character recited in claim 15 in which said plurality of second gating means are coupled to receive sequentially occurring gating signals, respectively, to sequentially render said second gating means conductive thereby sequentially transmitting data signals from said dZ-outputs of said respective integrators to said data bus means.

Claim 24

A programmable digital differential analyzer of the character recited in claim 17 in which said programmable means comprises a plurality of timing means coupled to said plurality of first and third gating means, respectively, for providing predetermined timing signals concurrently with said gating signals for selectively rendering said plurality of first and third gating means conductive, thereby effecting predetermined interconnections among said dZ-outputs and said dX and dY-inputs in accordance with said predetermined timing signals.

Claim 25

A programmable digital differential analyzer of the character recited in claim 18 in which each said timing means comprises shift register means for sequentially providing signals representative of the bits of a predetermined digital number stored therein, thereby providing said timing signals.

Claim 26

A programmable digital differential analyzer of the character recited in claim 19 in which said programmable means further includes means for changing said stored digital numbers thereby changing the effective interconnections among said integrators.

Claim 27

A programmable digital differential analyzer of the character recited in claim 20 in which all of said means are disposed on a common substrate.

Claim 28

A programmable digital differential analyzer of the character recited in claim 20 in which all of said means form a single monolithic semiconductor circuit.