Commutation circuit for scr{3 s

Claim 2

An inverter circuit comprising a pair of input conductors for receiving a unidirectional energizing potential, a series circuit coupled between the input conductors comprising at least one SCR, a commutating choke assembly having first and second windings electrically and magnetically coupled to each other, with a common connection between the first and second windings, a first commutating capacitor coupled between one of the input conductors and said common connection, a second commutating capacitor coupled to said one input conductor, and a first inductor, coupled between said common connection and the second commutating capacitor, such that in the commutation of the SCR, the first commutating capacitor initially discharges through one of the commutating choke windings, and thereafter the second commutating capacitor discharges through the inductor and said one winding of the commutating choke.

Claim 3

An inverter circuit as claimed in claim 1 and further comprising a third commutating capacitor coupled to said one input conductor, and a second inductor, coupled between said third commutating capacitor and the common connection between the first inductor and the second commutating capacitor, further to reduce the amount of energy required to commutate the SCR.

Claim 4

In an inverter circuit comprising a pair of input conductors for receiving a unidirectional energizing potential, a series circuit coupled between the input conductors comprising a first SCR, a commutating choke assembly having first and second windings electrically and magnetically coupled to each other, with a common connection between the first and second windings, and a second SCR, a first commutating capacitor coupled between one of the input conductors and said common connection, a second commutating capacitor coupled between said common connection and the other of the input conductors, third and fourth commutating capacitors coupled in series between the input conductors, and a first inductor coupled between said common connection and a common connection between the third and fourth commutating capacitors, such that upon conduction of one SCR, one of the first and second commutating capacitors initially discharges through the associated commutating choke winding, and thereafter the corresponding one of the third and fourth commutating capacitors discharges through the first inductor and said associated commutating choke winding.

Claim 5

In an inverter circuit comprising a pair of input conductors for receiving a unidirectional energizing potential, a series circuit coupled between the input conductors comprising a first SCR, a commutating choke assembly having first and second windings electrically and magnetically coupled to each other, with a common connection between the first and second windings, and a second SCR, a first commutating capacitor coupled between one of the input conductors and said common connection, a second commutating capacitor coupled between said common connection and the other of the input conductors, third and fourth commutating capacitors coupled in series between the input conductors, and a first inductor coupled between said common connection and a common connection between the third and fourth commutating capacitors, such that upon conduction of one SCR, one of the first and second commutating capacitors initially discharges through the associated commutating choke winding, and thereafter the corresponding one of the third and fourth commutating capacitors discharges through the first inductor and said associated commutating choke winding.

Claim 6

An inverter circuit as claimed in claim 3 and further comprising fifth and sixth commutating capacitors coupled in series between the input conductors, and a second inductor coupled between the common connection of the fifth and sixth commutating capacitors and the common connection between the third and fourth commutating capacitors, further to decrease the amount of energy required to commutate one of the SCR''s.

Claim 7

An inverter circuit connected for energization over a pair of input conductors, comprising a series circuit coupled between the input conductors, including a first silicon controlled rectifier, a second silicon controlled rectifier, and a commutating choke assembly having first and second windings electrically and magnetically coupled to each other, a first commutating capacitor, connected to receive energy over a first energizing conductor and, upon gating on of the first silicon controlled rectifier, to discharge the stored energy into the first commutating choke winding, a second commutating capacitor, connected to receive energy over a second energizing conductor and, upon gating on of the second silicon controlled rectifier, to discharge the stored energy into the second commutating choke winding, and third and fourth commutating capacitors coupled in series between the energizing conductors, and a first inductor coupled between the common connection of the third and fourth commutating capacitors and the first and second cOmmutating capacitors, such that upon conduction of one silicon controlled rectifier, one of the first and second commutating capacitors initially discharges through the associated commutating choke winding, and thereafter the corresponding one of the third and fourth commutating capacitors discharges through the first inductor and said associated commutating choke winding.

Claim 8

An inverter circuit connected for energization over a pair of input conductors, comprising a series circuit coupled between the input conductors, including a first silicon controlled rectifier, a second silicon controlled rectifier, and a commutating choke assembly having first and second windings electrically and magnetically coupled to each other, a first commutating capacitor, connected to receive energy over a first energizing conductor and, upon gating on of the first silicon controlled rectifier, to discharge the stored energy into the first commutating choke winding, a second commutating capacitor, connected to receive energy over a second energizing conductor and, upon gating on of the second silicon controlled rectifier, to discharge the stored energy into the second commutating choke winding, and third and fourth commutating capacitors coupled in series between the energizing conductors, and a first inductor coupled between the common connection of the third and fourth commutating capacitors and the first and second cOmmutating capacitors, such that upon conduction of one silicon controlled rectifier, one of the first and second commutating capacitors initially discharges through the associated commutating choke winding, and thereafter the corresponding one of the third and fourth commutating capacitors discharges through the first inductor and said associated commutating choke winding.

Claim 9

An inverter circuit as claimed in claim 5 and further comprising fifth and sixth commutating capacitors coupled in series between the energizing conductors, and a second inductor coupled between the common connection of the fifth and sixth commutating capacitors and the common connection between the third and fourth commutating capacitors, further to decrease the amount of energy required to commutate one of the silicon controlled rectifiers.

Claim 10

An inverter circuit comprising a pair of input conductors for receiving a first DC voltage, a power transfer circuit including at least one SCR coupled between the input conductors, and a commutating circuit, coupled to said SCR, comprising means for receiving a second DC voltage, switching means for applying said second DC voltage to the SCR as a commutating pulse in the appropriate sense to commutate the SCR, and circuit means for shaping the commutating pulse to minimize the amount of energy expended in the commutation.

Claim 11

An inverter circuit comprising a pair of input conductors for receiving a first DC voltage, a power transfer circuit including at least one SCR coupled between the input conductors, and a commutating circuit, coupled to said SCR, comprising means for receiving a second DC voltage, switching means for applying said second DC voltage to the SCR as a commutating pulse in the appropriate sense to commutate the SCR, and circuit means for shaping the commutating pulse to minimize the amount of energy expended in the commutation.

Claim 12

An inverter circuit as claimed in claim 7 in which the circuit means in the commutating circuit comprises a first capacitor, an inductor having one end coupled to one plate of the first capacitor and a second capacitor having one plate coupled to the other end of the inductor and the other plate coupled to the other plate of the first capacitor, which capacitors are charged to approximately the second DC voltage level prior to actuation of the switching means such that upon actuation of the switching means, the first commutating capacitor initially discharges as the inductor retards discharge of the second capacitor, and thereafter the second commutating capacitor discharges.

Claim 13

An inverter circuit comprising a pair of input conductors for receiving a unidirectional energizing potential, a series circuit coupled between the input conductors comprising at least one SCR, a commutating choke assembly having first and second windings electrically and magnetically coupled to each other, with a common connection between the first and second windings, means including a precharge conductor for supplying a commutating potential, a first commutating capacitor coupled to said common connection, a second commutating capacitor, and a first inductor, coupled between said common connection and the second commutating capacitor and further coupled to said precharge conductor to complete a charging circuit for the first and second commutating capacitors, such that in the commutation of the SCR, the first commutating capacitor initially discharges through one of the commutating choke windings, and thereafter the second commutating capacitor discharges through the inductor and said one winding of the commutating choke.

Claim 14

An inverter circuit comprising a pair of input conductors for receiving a unidirectional energizing potential, a series circuit coupled between the input conductors comprising at least one SCR, a commutating choke assembly having first and second windings electrically and magnetically coupled to each other, with a common connection between the first and second windings, means including a precharge conductor for supplying a commutating potential, a first commutating capacitor coupled to said common connection, a second commutating capacitor, and a first inductor, coupled between said common connection and the second commutating capacitor and further coupled to said precharge conductor to complete a charging circuit for the first and second commutating capacitors, such that in the commutation of the SCR, the first commutating capacitor initially discharges through one of the commutating choke windings, and thereafter the second commutating capacitor discharges through the inductor and said one winding of the commutating choke.

Claim 15

An inverter circuit as claimed in claim 9, further comprising a third commutating capacitor, and a second inductor, coupled between said third commutating capacitor and the common connection between the first inductor and the second commutating capacitor, further to reduce the amount of energy required to commutate the SCR.