Patent US3594551A successfully refreshed from Google Patents.
US3594551A
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High speed digital counter
Assignee: Raytheon Co
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Filing: 1966-11-29
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Granted: 1971-07-20
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Expires: 1986-11-29
Abstract
Abstract The input pulses to be counted are supplied to a bit gate and from there are passed to a Divide-by-N circuit. The output of the Divide-by-N circuit is supplied to both a Divide-by-N circuit and back to the bit gate. The pulse being resupplied to the bit gate is employed to inhibit one pulse from passing through the bit gate. After N input pulses have been received, one pulse is inhibited and a one count is recorded by the Divide-by-M register. This process continues until the Divide-by-M register has recorded a number of input pulses equal to the least significant digit of the count. The bit gate is then disabled from subtracting any further pulses during the remainder of the count.
Inventors
- 👤 Harry D Shearer
- 👤 James R Strain
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:08
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/662
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
178 words
The method for counting a predetermined number of pulses in a pulse train sequence, comprising storing a preselected number less than the predetermined total pulse count, passing said input pulse train through subtraction means for producing a modified pulse train at the output of said subtraction means by subtracting a number of said input pulses corresponding in number to said stored preselected number, said pulse subtraction step comprising repeatedly counting said modified pulses in a cyclic cOunter which provides an output signal each time a reference counting state is obtained, initially suppressing one pulse of said input pulses train in said subtractor means responsive to each output pulse produced by said cyclic counter, counting the output signals produced by said cyclic counter, comparing the number of counted output pulses produced by said cyclic counter during a pulse-counting cycle of operation with said stored preselected number, and inhibiting said subtractor means from suppressing any further pulses from the input pulse train after the counted number of output pulses produced by said cyclic counter first equals said stored preselected number.
Claim 2
Independent Claim
178 words
The method for counting a predetermined number of pulses in a pulse train sequence, comprising storing a preselected number less than the predetermined total pulse count, passing said input pulse train through subtraction means for producing a modified pulse train at the output of said subtraction means by subtracting a number of said input pulses corresponding in number to said stored preselected number, said pulse subtraction step comprising repeatedly counting said modified pulses in a cyclic cOunter which provides an output signal each time a reference counting state is obtained, initially suppressing one pulse of said input pulses train in said subtractor means responsive to each output pulse produced by said cyclic counter, counting the output signals produced by said cyclic counter, comparing the number of counted output pulses produced by said cyclic counter during a pulse-counting cycle of operation with said stored preselected number, and inhibiting said subtractor means from suppressing any further pulses from the input pulse train after the counted number of output pulses produced by said cyclic counter first equals said stored preselected number.
Claim 3
Dependent Claim
30 words
The method as in claim 1, wherein the preselected number of pulses subtracted from the input pulse train corresponds to the least significant digit of said predetermined number of pulses.
Claim 4
Dependent Claim
126 words
A high-speed digital counter for counting a predetermined number of pulses in an input pulse train sequence, comprising cyclic-counting means, selective pulse suppression means disposed intermediate the input pulse train and said cyclic-counting means, said cyclic means including means for supplying an output signal each time a reference state is attained thereby, additional counting means connected to said cyclic counting means, means included in said selective pulse suppression means selectively responsive to an output from said cyclic-counting means for suppressing a pulse from said input pulse train, and comparator means responsive to a particular count state in said additional counting means first attaining a preselected number during a composite counting cycle for inhibiting any further pulse suppression by said pulse suppression means during the pulse-counting cycle.
Claim 5
Dependent Claim
126 words
A high-speed digital counter for counting a predetermined number of pulses in an input pulse train sequence, comprising cyclic-counting means, selective pulse suppression means disposed intermediate the input pulse train and said cyclic-counting means, said cyclic means including means for supplying an output signal each time a reference state is attained thereby, additional counting means connected to said cyclic counting means, means included in said selective pulse suppression means selectively responsive to an output from said cyclic-counting means for suppressing a pulse from said input pulse train, and comparator means responsive to a particular count state in said additional counting means first attaining a preselected number during a composite counting cycle for inhibiting any further pulse suppression by said pulse suppression means during the pulse-counting cycle.
Claim 6
Dependent Claim
27 words
A combination as in claim 3 further comprising additional comparator means connected to said additional counter means for signaling the incidence of said predetermined number of pulses.
Claim 7
Dependent Claim
43 words
A combination as in claim 4 wherein additional comparator means further comprises means for restoring said pulse suppression means to a pulse suppression mode of operation, and for resetting said additional counting means responsive to the incidence of said predetermined number of pulses.
Claim 8
Dependent Claim
22 words
A combination as in claim 3 wherein said preselected number of pulses corresponds to the least significant digit of said predetermined count.
Claim 9
Dependent Claim
69 words
A combination as in claim 3 wherein said selective pulse suppression means comprises bit gate means including means for passing said input pulse train through said bit gate means, means responsive to a pulse from said cyclic-counting means for suppressing a pulse in said pulse train, and means responsive to the next pulse in said train for permitting said pulse and succeeding pulses in said pulse train to pass.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-19 | 1975-01-18 | 1975-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-19 | 1979-01-18 | 1979-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-19 | 1983-01-18 | 1983-07-20 | $7700.00 | Window Closed / Lapsed |