Electrically alterable digital differential analyzer

Claim 2

An electrically alterable digital differential analyzer comprising the combination of a pluraLity of computational elements, each of which includes an output inputs, a plurality of electrical conductor means, each being associated with a different group of computational elements within the plurality of computational elements, separate means coupled between each of the electrical conductor means and the outputs of the computational elements within the associated group for multiplexing signals at the outputs onto the associated electrical conductor means in predetermined order, means for providing a plurality of signal conditions which identify the particular ones of the electrical conductor means carrying signals to be applied as input signals to the computational elements, and means responsive to the signal conditions for substantially simultaneously coupling the inputs of selected ones of the computational elements to selected ones of the electrical conductor means.

Claim 3

An electrically alterable digital differential analyzer in accordance with claim 1, wherein the computational elements comprise integrators, each of which includes first and second registers, means for summing input signals which appear at selected ones of the inputs thereof, means responsive to the summing means for periodically adding the sum of the input signals to the first register in parallel word fashion, means coupled between the first and second registers for periodically transferring signals from the first register into the second register in parallel word fashion, said second register comprising a plurality of different register stages, each of which includes an output terminal, and further comprising means for providing a plurality of scaling signal conditions which identify a particular one of the output terminals of each integrator to be used to provide an output signal, and means coupled to the output terminals of each integrator and responsive to the scaling signal conditions to couple a selected one of the output terminals of each integrator to the multiplexing means as the integrator output.

Claim 4

An electrically alterable digital differential analyzer in accordance with claim 1, wherein the means for providing a plurality of signal conditions comprises means for generating signals which define a desired interconnection of the computational element inputs and the electrical conductor means for each of a series of signals provided by the computational elements to the outputs thereof, and a plurality of registers coupled to receive the generated signals, said registers assuming logical states in accordance with the values of the generated signals.

Claim 5

An electrically alterable digital differential analyzer in accordance with claim 3, wherein the means for generating signals which define a desired interconnection comprises a general purpose digital computer.

Claim 6

An electrically alterable digital differential analyzer in accordance with claim 1, wherein each of the separate means for multiplexing time multiplexes signals at the outputs of the associated group of computational elements onto the associated electrical conductor means, and further including means for providing a plurality of signal conditions which identify the time positions of the signals to be applied as input signals to the computational elements, and wherein the means for substantially simultaneously coupling the inputs of selected ones of the computational elements to selected ones of the electrical conductor means includes means associated with each of the inputs and responsive to the time position identification signal conditions to prevent the passage of signals from the selected ones of the electrical conductor means to the coupled inputs except during a selected time interval.

Claim 7

An electrically alterable digital differential analyzer in accordance with claim 5, wherein the computational elements comprise integrators and the electrical conductor means comprise buses.

Claim 8

An electrically alterable digital differential analyzer in accordance with claim 5, further including means for prOviding a plurality of inhibit signal conditions which identify those computational element inputs which are not to receive an input signal, and means for providing a plurality of sign change signal conditions which identify those computational element inputs which are to receive an input signal of reversed sign, and wherein the means for substantially simultaneously coupling the inputs of selected ones of the computational elements to selected ones of the electrical conductor means includes means associated with each of the inputs and responsive to the inhibit signal conditions to prevent the passage of all signals from the selected ones of the electrical conductor means to the coupled inputs, and means associated with each of the inputs and responsive to the sign change signal condition for changing the signs of the input signals thereto.

Claim 9

An electrically alterable digital differential analyzer comprising the combination of a plurality of computational elements which undergo successive iterations, each of the computational elements having an electrical output and a plurality of different electrical inputs, a plurality of buses, means for generating clock pulses, separate means coupled to the output of each computational element and responsive to a particular one of the clock pulses for time encoding signals from the output terminal of the associated computational element at the start of each iteration, separate means coupled between each bus and a different plurality of time encoding means and responsive to the clock pulses for multiplexing the time encoded signals from the associated time encoding means onto the associated one of the buses, and time and space decoding means coupled between each input of the computational elements and the buses, said time and space decoding means comprising a space domain selection program register for storing bit signals representing the particular one of the buses which carries the desired input signal for the associated input for each iteration, a time domain selection program register for storing bit signals representing the time position of the desired input signal for the associated input for each iteration, time position selection means coupled to the associated input and operative to pass a signal applied thereto to the associated input when enabled, means responsive to the bit signals stored by the space domain selection program register for decoding the information represented thereby, means responsive to the space decoding means and coupled to each of the buses for coupling a particular one of the buses to the time position selection means in accordance with the decoded information, means responsive to the bit signals stored by the time domain selection program register for generating a signal the time of occurrence of which corresponds to the information represented thereby, and gating means responsive to the clock pulses and the generated signal for enabling the time position selection means whenever the generated signal and a clock pulse coincide in time.

Claim 10

An electrically alterable digital differential analyzer comprising the combination of a plurality of computational elements which undergo successive iterations, each of the computational elements having an electrical output and a plurality of different electrical inputs, a plurality of buses, means for generating clock pulses, separate means coupled to the output of each computational element and responsive to a particular one of the clock pulses for time encoding signals from the output terminal of the associated computational element at the start of each iteration, separate means coupled between each bus and a different plurality of time encoding means and responsive to the clock pulses for multiplexing the time encoded signals from the associated time encoding means onto the associated one of the buses, and time and space decoding means coupled between each input of the computational elements and the buses, said time and space decoding means comprising a space domain selection program register for storing bit signals representing the particular one of the buses which carries the desired input signal for the associated input for each iteration, a time domain selection program register for storing bit signals representing the time position of the desired input signal for the associated input for each iteration, time position selection means coupled to the associated input and operative to pass a signal applied thereto to the associated input when enabled, means responsive to the bit signals stored by the space domain selection program register for decoding the information represented thereby, means responsive to the space decoding means and coupled to each of the buses for coupling a particular one of the buses to the time position selection means in accordance with the decoded information, means responsive to the bit signals stored by the time domain selection program register for generating a signal the time of occurrence of which corresponds to the information represented thereby, and gating means responsive to the clock pulses and the generated signal for enabling the time position selection means whenever the generated signal and a clock pulse coincide in time.

Claim 11

An electrically alterable digital differential analyzer in accordance with claim 8, further including means for providing signals which represent programmed interconnections of the computational element inputs and outputs, and logic means coupled to the space and time domain program registers and responsive to the programmed interconnection signals for selecting the states of the program registers in accordance with a particular logic scheme.

Claim 12

An electrically alterable digital differential analyzer in accordance with claim 8, wherein the computational elements comprise integrators, each of which includes a register having a plurality of stages with output coupled thereto, means for coupling a selected one of the output lines to the time encoding means as the output of the computational element, means for selectively preventing passage of input signals to different ones of the computational element inputs, and means for selectively reversing the polarity of input signals to different ones of the computational element inputs.

Claim 13

An integrator comprising the combination of a first register having a plurality of stages for storing a quantity Y, a second register having a plurality of stages for storing a quantity R, means for serially loading initial conditions into the first register, means for summing a plurality of dependent incremental values dy received during each iteration of the integrator, means for adding the sum of the dy values received during a particular iteration to the quantity Y in whole number form, means coupling at least some of the stages of the first register to different ones of the stages of the second register, and means for transferring the quantity Y into the second register via the interconnected stages of the registers in parallel word fashion under the control of an independent incremental value dx during the particular iteration.

Claim 14

An integrator comprising the combination of a first register having a plurality of stages for storing a quantity Y, a second register having a plurality of stages for storing a quantity R, means for serially loading initial conditions into the first register, means for summing a plurality of dependent incremental values dy received during each iteration of the integrator, means for adding the sum of the dy values received during a particular iteration to the quantity Y in whole number form, means coupling at least some of the stages of the first register to different ones of the stages of the second register, and means for transferring the quantity Y into the second register via the interconnected stages of the registers in parallel word fashion under the control of an independent incremental value dx during the particular iteration.

Claim 15

An integrator in accordance with claim 11, wherein each of the stages of the first and second registers comprises a bistable memory element and an associated logic circuit including a full adder, each logic circuit being coupled to set the state of the associated memory element in accordance with the sum of an input signal, a signal representing the present state of the memory element, and a carry signal from the logic circuit of the next least significant bit stage of the register.

Claim 16

An integrator in accordance with claim 11, wherein the means for summing a plurality of dependent incremental values dy provides first and second bits representing the value of the sum of the dy values and a third bit representing the sign of the value of the sum of the dy values, and the means for adding the sum of the dy values to the quantity Y in whole number form includes means for entering the first and second bits into the two least significant stages of the first register, and means for entering the third bit into all other stages of the first register.

Claim 17

In an integrator wherein at least one dependent incremental variable dy is algebraically added to a first register to update a quantity Y stored therein and the updated value of Y transferred into a second register under the control of an independent incremental variable dx during each iteration of the integrator, means for selectively changing the quantity stored within the second register to perform a higher order correction for each updated value of Y comprising means for storing the dy and dx variables which are received during each iteration of the integrator, means for weighting the stored values of dy in accordance with the values of the stored dx incremental variables during a subsequent iteration, and means for algebraically adding the weighted values of dy to the quantity stored within the second register during the subsequent iteration.

Claim 18

In an integrator wherein at least one dependent incremental variable dy is algebraically added to a first register to update a quantity Y stored therein and the updated value of Y transferred into a second register under the control of an independent incremental variable dx during each iteration of the integrator, means for selectively changing the quantity stored within the second register to perform a higher order correction for each updated value of Y comprising means for storing the dy and dx variables which are received during each iteration of the integrator, means for weighting the stored values of dy in accordance with the values of the stored dx incremental variables during a subsequent iteration, and means for algebraically adding the weighted values of dy to the quantity stored within the second register during the subsequent iteration.

Claim 19

The improvement defined in claim 14 above, wherein a separate dx incremantal variable is stored for each higher order to which a particular updated value of Y is to be corrected, the values of dy being weighted and algebraically added to the quantity stored within the second register.

Claim 20

The improvement defined in claim 14 above, wherein the at least one dependent incremental variable dy is algebraically added to the first register in parallel word fashion, the updated value of Y is transferred into the second register in parallel word fashion, and the weighted values of dy are added to the second register in parallel word fashion.

Claim 21

An integrator comprising the combination of a first register for storing a quantity Y, a second register for storing a quantity R, said first and second registers each comprising a plurality of different bit stages of ascending binary significance, means for receiving a plurality of dependent incremental values dy during each iteration of the integrator, means for adding the dy values received during a particular iteration to the quantity Y, means coupling at least some of the stages of the first register to different ones of the stages of the second register, means for transferring the quantity Y into the second register via the interconnected stages of the registers in parallel word fashion under the control of an independent incremental value dx during the particular iteration, means for storing the preceding incremental nonzero values dx, and means for adding weighted values of dy to the quantity R under the control of the stored values of the preceding nonzero dx value.

Claim 22

An integrator comprising the combination of a first register for storing a quantity Y, a second register for storing a quantity R, said first and second registers each comprising a plurality of different bit stages of ascending binary significance, means for receiving a plurality of dependent incremental values dy during each iteration of the integrator, means for adding the dy values received during a particular iteration to the quantity Y, means coupling at least some of the stages of the first register to different ones of the stages of the second register, means for transferring the quantity Y into the second register via the interconnected stages of the registers in parallel word fashion under the control of an independent incremental value dx during the particular iteration, means for storing the preceding incremental nonzero values dx, and means for adding weighted values of dy to the quantity R under the control of the stored values of the preceding nonzero dx value.

Claim 23

A digital differential analyzer comprising a plurality of integrators, at least some of which include a register having a plurality of flip-flops and an associated plurality of full adders, each flip-flop and an associated full adder defining a different bit stage of the register, means for normally interconnecting the full adders and flip-flops to effect a parallel word operation of the register, said interconnecting means comprising means for interconnecting each flip-flop and an associated full adder such that the full adder controls the new stage of the flip-flop by determining the sum of a signal representing the present state of the flip-flop, an input signal, and a carry signal which may be provided by the full adder of the next less significant bit stage, and means for coupling each full adder to the full adder of the next more significant bit stage such that a carry signal which may be generating in each stage is passed to the next stage.

Claim 24

A digital differential analyzer comprising a plurality of integrators, at least some of which include a register having a plurality of flip-flops and an associated plurality of full adders, each flip-flop and an associated full adder defining a different bit stage of the register, means for normally interconnecting the full adders and flip-flops to effect a parallel word operation of the register, said interconnecting means comprising means for interconnecting each flip-flop and an associated full adder such that the full adder controls the new stage of the flip-flop by determining the sum of a signal representing the present state of the flip-flop, an input signal, and a carry signal which may be provided by the full adder of the next less significant bit stage, and means for coupling each full adder to the full adder of the next more significant bit stage such that a carry signal which may be generating in each stage is passed to the next stage.

Claim 25

A digital differential analyzer in accordance with claim 18, wherein said at least some of the integrators further comprise means coupled to receive a plurality of incremental input signals for generating a plurality of bit signals, one of which represents the sign of the sum of the incremental input signals and the others of which represent the value of the sum of the incremental input signals, and means for simultaneously applying each value bit signal to a different one of the full adders of the less significant bit stages of the register as input signals thereto and the sign bit signal to the full adders of the remaining more significant bit stages of the register as input signals thereto.

Claim 26

A digital differential analyzer in accordance with claim 18, wherein said at least some of the integrators further comprise means for selectively interconnecting the inputs and outputs of the flip-flops within successive stages of the register to effect a serial shift mode of operation.

Claim 27

A digital differential analyzer in accordance with claim 20, wherein said at least some of the integrators further comprise means for selectively coupling the output of the flip-flop within the most significant bit stage of the register to the input of the flip-flop within the least significant bit stage of the register to effect a recirculation of the information stored within the flip-flops during a readout mode of operation.

Claim 28

A digital differential analyzer in accordance with claim 18, wherein said at least some of the integrators further comprise a second register having a plurality of flip-flops and an associated plurality of full adders, each flip-flop and an associated full adder defining a different bit stage of the register, means for interconnecting the full adders and flip-flops to effect a parallel word operation of the register, said interconnecting means comprising means for interconnecting each flip-flop and associated full adder such that the full adder controls the new state of the flip-flop by determining the sum of a signal representing the present state of the flip-flop, an input signal, and a carry signal which may be provided by the full adder of the next less significant bit stage, and means for coupling each full adder to the next more significant bit stage such that a carry signal which may be generated in each stage is passed to the next stage, and further comprising meanS responsive to the receipt of an independent incremental value for coupling the outputs of at least some of the flip-flops within the first register to pass signals representing the states thereof as input signals to the at least some of the full adders within the second register to effect a transfer of information therebetween in parallel word fashion.

Claim 29

A digital differential analyzer in accordance with claim 22, further including means coupled to the carry output of a selected one of the full adders in the second register for providing an incremental output signal from the integrator, a plurality of buses, means coupled to receive the output signal for multiplexing the signal onto a selected one of the buses, and at least one means coupled to all of the buses for passing a signal carried by a selected one of the buses to the integrator as a dependent incremental input value.

Claim 30

A digital differential analyzer in accordance with claim 22, wherein the means for coupling the outputs of at least some of the flip-flops includes means for passing signals representing the actual values of the states of the flip-flops to the at least some of the full adders within the second register to effect a direct addition of the value stored in the first register to that stored in the second register whenever the independent incremental value is a positive value, and means for passing signals representing the two''s complement of the states of the flip-flops to the at least some of the full adders within the second register to effect a subtraction of the value stored in the first register from that stored in the second register whenever the independent incremental value is a negative value, the means for passing signals representing the two''s complement comprising means for inverting the signals appearing at the outputs of the at least some of the flip-flops in the first register to form the one''s complement thereof, and means for adding a bit signal to the least significant bit stage of the second register.

Claim 31

A digital differential analyzer in accordance with claim 22, wherein the second register includes a stage representing a bit which is lower in significance than the bit represented by the least significant stage of the first register, and further comprising means coupled to receive a plurality of incremental input signals for generating a plurality of bit signals representative of the sum thereof, the least significant one of the generated bit signals being transferred into the least significant bit stage of the second register to implement a trapezoidal correction of the value previously transferred from the first register into the second register.