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US3585604A
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Calculating machines
Assignee: Bell Punch Co Ltd
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Filing: 1969-01-17
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Granted: 1971-06-15
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Expires: 1989-01-17
Abstract
Abstract A calculating machine wherein several shift registers store numbers. Each shift register has a buffer stage with gating means. Pulse trains are introduced at the gating means as input pulses for controlling the outputs of the shift registers.
Inventors
- 👤 John George Lloyd
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:51
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/491; G06F7/498; G06F7/4981
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
160 words
A calculating machine having a number store register with a plurality of stages comprising a plurality of multistage shift registers with a shift register buffer stage connected to process output signals from each multistage shift register, an input of each of the shift register buffer stages being connected to a source of trains of digit pulses; a plurality of gate circuits, the output of a gate circuit being connected to the input of a shift register buffer stage connected to the source of trains of digit pulses, the inputs of the gate circuits being connected in a logic sequence to the outputs of the shift register buffer stages; whereby, when a train of digit pulses is applied to the inputs of the plurality of shift register buffer stages, the gate circuits operate in accordance with the logic sequence to control the entry of the pulse count of the train of digit pulses into the plurality of shift register buffer stages.
Claim 2
Dependent Claim
160 words
A calculating machine having a number store register with a plurality of stages comprising a plurality of multistage shift registers with a shift register buffer stage connected to process output signals from each multistage shift register, an input of each of the shift register buffer stages being connected to a source of trains of digit pulses; a plurality of gate circuits, the output of a gate circuit being connected to the input of a shift register buffer stage connected to the source of trains of digit pulses, the inputs of the gate circuits being connected in a logic sequence to the outputs of the shift register buffer stages; whereby, when a train of digit pulses is applied to the inputs of the plurality of shift register buffer stages, the gate circuits operate in accordance with the logic sequence to control the entry of the pulse count of the train of digit pulses into the plurality of shift register buffer stages.
Claim 3
Dependent Claim
67 words
A calculating machine according to claim 1, wherein each stage of said plurality of shift register buffer stages and the stages of the multistage shift registers include bistable circuits which are connected to a source of shift pulses, the frequency of the digit pulses from the trains of digit pulses being at least ten times the frequency of the shift pulses from the source of shift pulses.
Claim 4
Dependent Claim
118 words
A calculating machine according to claim 2, wherein the number store register further comprises a two-input AND gate, one input on the gate being connected to the source of trains of digit pulses the other input being connected to a source of clock pulses, the frequency of the clock pulses and the digit pulses being the same, the frequency of the clock pulses from the source of clock pulses being at least ten times the frequency of the shift pulses from the source of shift pulses, and an output amplifier whose input is connected to the output of the AND gate circuit and whose output is connected to the input of the plurality of shift register buffer stages.
Claim 5
Dependent Claim
79 words
A calculating machine according to claim 1, wherein the number store register further comprises a plurality of amplifier circuits which correspond in number to number of outputs of the plurality of multistage registers, the input to an amplifier circuit being connected to an output of a shift register buffer stage and the output of the amplifier circuit being connected to the input of that multistage shift register to which the output of the shift register buffer circuit is connected.
Claim 6
Dependent Claim
32 words
A calculating machine according to claim 1, wherein the number store register further comprises a decoder means whose input is connected to the outputs of the plurality of shift register buffer stages.
Claim 7
Dependent Claim
77 words
A calculating machine according to claim 5, wherein the decoder means comprises a decimal decoder matrix whose inputs are connected to the outputs of the plurality of shift register buffer stages respectively and whose outputs are ten lines which corresponding to the decimal digits; whereby, when a pulse count is stored in the plurality of shift register buffer stages, the decoder matrix energizes the output lines corresponding to the decimal digit corresponding to the stored pulse count.
Claim 8
Dependent Claim
57 words
A calculating machine according to claim 1, wherein each number stage the plurality of said multistage shift registers connected to a respective shift register buffer stage comprises a plurality of binary processing units connected in a circulating loop which represents a binary weight of the binary code for a decimal digit number stored in that number stage.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-14 | 1974-12-14 | 1975-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-14 | 1978-12-14 | 1979-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-14 | 1982-12-14 | 1983-06-15 | $7700.00 | Window Closed / Lapsed |