Patent US3581291A successfully refreshed from Google Patents.
US3581291A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory control system in multiprocessing system
Assignee: Hitachi Ltd
•
Filing: 1969-10-29
•
Granted: 1971-05-25
•
Expires: 1989-10-29
Abstract
Abstract A multiprocessing system comprises two processors and a main memory to be utilized by the processors in common. Each processor is provided with a buffer memory which stores information read from the main memory, block by block, and the main memory is provided with a key memory which stores an indicator indicating whether or not information in the main memory is read out and stored in each processor at each predetermined amount of its capacity (sector). When one of the processors carries out a writing in a sector of the main memory, whether or not the information of the sector is stored in the other processor is checked. When the information is stored, the address of the information is supplied to the other processor to invalidate the corresponding sector of the buffer memory. In this manner, the incoincidence between the stored contents of the main memory and buffer memory is prevented.
Inventors
- 👤 Shoji Iwamoto
- 👤 Hisashi Horikoshi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:48
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/12; G06F12/121; G06F12/123; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
149 words
A memory control system in a multiprocessing system including a plurality of information handling units, and a main memory to which said information handling units are accessible in common, at least one of said information handling units being a processor provided with buffer memory means for storing the information read out from said main memory block by block, comprising a key memory for storing indicators each indicating whether or not information in said main memory is read out at each predetermined capacity and stored in said buffer memory means, means for setting the indicator corresponding to said predetermined capacity including said information in said key memory each time information is read out from said main memory, and means for checking the indicator corresponding to said information in said key memory each time information in said main memory is rewritten to make said information in said buffer memory means invalid.
Claim 2
Dependent Claim
149 words
A memory control system in a multiprocessing system including a plurality of information handling units, and a main memory to which said information handling units are accessible in common, at least one of said information handling units being a processor provided with buffer memory means for storing the information read out from said main memory block by block, comprising a key memory for storing indicators each indicating whether or not information in said main memory is read out at each predetermined capacity and stored in said buffer memory means, means for setting the indicator corresponding to said predetermined capacity including said information in said key memory each time information is read out from said main memory, and means for checking the indicator corresponding to said information in said key memory each time information in said main memory is rewritten to make said information in said buffer memory means invalid.
Claim 3
Dependent Claim
60 words
A memory control system according to claim 1, in which said indicator checking means comprises means for reading out the indicator specified by the address of the information to be written in said key memory, and means for supplying a control signal to make said information invalid to said buffer memory means when the read out indicator is turned on.
Claim 4
Dependent Claim
119 words
A memory control system according to claim 1, in which each of said buffer memory means comprises a buffer memory composed of a plurality of sectors each consisting of a plurality of blocks, an associative register for storing the most significant bits of the address signals of the information stored in said sectors and block indiCators each of which indicates the blocks storing valid information in said sector, means for comparing the most significant bits of an address signal fed from said processor and the most significant bits of the address signals stored in said associative register for checking, and means for checking said block indicators in accordance with the bits corresponding to the block of said address signal.
Claim 5
Dependent Claim
49 words
A memory control system according to claim 1, in which each of a plurality of ones of said information handling units comprises a processor including buffer memory means which reads out the information from said main memory and stores the information in said buffer memory means block by block.
Claim 6
Dependent Claim
32 words
A memory control system according to claim 1, in which said information handling units include at least one of I/O devices, I/O channels, transmission control units, and processors having no buffer memory.
Claim 7
Dependent Claim
52 words
A memory control system according to claim 3, comprising means for supplying, when said information in said sector of said buffer memory is to be replaced by fresh information in another sector, the address signal of said replaced information to said key memory to reset the corresponding indicator in said key memory.
Claim 8
Dependent Claim
57 words
A memory control system according to claim 4, in which each of said indicators stored in said key memory comprises a plurality of bits provided correspondingly to said buffer memory means for indicating whether or not information in said main memory is read out from said main memory and stored in each of said buffer memory means.
Claim 9
Dependent Claim
51 words
A memory control system according to claim 7, comprising means for checking said indicator comprised of said bits and for supplying, when buffer memory means other than that which made a write request stores the information, a control signal which invalidates said information to said buffer memory means storing said information.
Claim 10
Dependent Claim
142 words
A memory control system in a multiprocessing system comprising a plurality of processors, a main memory to which said processors are accessible in common, a plurality of buffer memory means provided correspondingly to said processors for storing the information read out from said main memory block by block, a key memory for storing indicators each indicating whether or not information in each predetermined capacity of said main memory is read out from said main memory and stored in said buffer memory means, means for setting said indicator in said key memory corresponding to said predetermined capacity including said information each time information in said main memory is read out, and means for invalidating said information in said buffer memory means by reading out the indicator corresponding to said information in said key memory each time information in said main memory is rewritten.
Claim 11
Dependent Claim
142 words
A memory control system in a multiprocessing system comprising a plurality of processors, a main memory to which said processors are accessible in common, a plurality of buffer memory means provided correspondingly to said processors for storing the information read out from said main memory block by block, a key memory for storing indicators each indicating whether or not information in each predetermined capacity of said main memory is read out from said main memory and stored in said buffer memory means, means for setting said indicator in said key memory corresponding to said predetermined capacity including said information each time information in said main memory is read out, and means for invalidating said information in said buffer memory means by reading out the indicator corresponding to said information in said key memory each time information in said main memory is rewritten.
Claim 12
Dependent Claim
57 words
A memory control system according to claim 9, in which each of said indicators stored in said key memory comprises a plurality of bits provided correspondingly to said buffer memory means for indicating whether or not information in said main memory is read out from said main memory and stored in each of said buffer memory means.
Claim 13
Dependent Claim
119 words
A memory control system according to claim 9, in which each of said buffer memory means comprises a buffer memory composed of a plurality of sectors each consisting of a plurality of blocks, an associative register for storing the most significant bits of the address signals of the information stored in said sector and block indicators each of which indicates the block storing valid information in said sector, means for comparing the most significant bits of an address signal fed from said processor and the most significant bits of the address signals stored in said associative register for checking, and means for checking said block indicators in accordance with the bits corresponding to the block of said address signal.
Claim 14
Dependent Claim
51 words
A memory control system according to claim 10, comprising means for checking said indicator comprised of said bits and for supplying, when buffeR memory means other than that which made a write request stores the information, a control signal which invalidates said information to said buffer memory means storing said information.
Claim 15
Dependent Claim
52 words
A memory control system according to claim 11, comprising means for supplying, when said information in said sector of said buffer memory is to be replaced by fresh information in another sector, the address signal of said replaced information to said key memory to reset the corresponding indicator in said key memory.
References Cited (Backward Citations)
US3248702A
Cited
US3218611A
Cited
US3339183A
Cited
US3422401A
Cited
US3387274A
Cited
US3395392A
Cited
US3435420A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-24 | 1974-11-23 | 1975-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-24 | 1978-11-23 | 1979-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-24 | 1982-11-23 | 1983-05-25 | $7700.00 | Window Closed / Lapsed |