US3579105A
Expired / Lapsed
US
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Digital readout system having an automatic zero-setting circuit
Assignee: Applied Biosystems Inc
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Filing: 1969-03-03
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Granted: 1971-05-18
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Expires: 1989-03-03
Abstract
Abstract A digital measuring circuit for determining a desired mathematical relationship between a first variable input signal and a second relatively constant ''''reference'''' signal includes in addition to the main or computing mode of operation, a second mode of operation for automatically recalibrating the computing circuit. The automatic recalibration is accomplished by supplying at the first input (where the normally variable signal would be applied) a ''''blank'''' input which is ''''expected'''' to be equal to the second ''''reference'''' input. The automatic recalibration circuit mode then causes a change in the effective amplitude value (as by attenuation, for example) of the ''''reference'''' signal, so as to create a balance or calibration between the ''''blank'''' first signal and the changed ''''reference'''' signal (for example making them equal). A ''''memory'''' stores the type of change (e.g., the attenuation factor of the ''''reference'''' input) necessary to create this balanced condition, and this stored calibration information is utilized during the normal computing mode so as to automatically calibrate out any systematic and other errors, even if they originate in the remote effective sources of either of the first variable signal or of the second ''''reference'''' signal. The circuit is disclosed in an exemplary embodiment particularly adapted to measuring the relative intensities of the ''''sample'''' and the ''''reference'''' beam intensities of a double-beam absorption spectrophotometer. In this exemplary usage, the computed relationship is the logarithm of the ratio of the reference beam intensity to that of the sample beam intensity, and the automatic calibration is accomplished (in a linear mode) by causing the ''''reference beam'''' intensity signal to be made equal to a ''''blank'''' first signal representing the intensity of the ''''sample beam'''' when no absorbing sample material is actually present in this beam. In such an environment, the computed logarithm of the ratio of the two signals may be obtained directly in ''''absorbance'''' units, or by further (manual) calibration of the computing circuit directly in terms of the concentration of the (absorbing component of the) sample material.
Inventors
- 👤 Larkin B Scott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:42
CPC Classifications
G; G06; G06J; G06J1/00
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
236 words
In a measuring circuit for determining a desired mathematical relationship between a first variable signal and a second signal, comprising: a first signal input means; a second signal input means; said first and second input means being common inputs to a first computing circuit and a second calibrating circuit; said first circuit comprising means for computing said desired mathematical relationship between said first and second signals applied to said first and second input means respectively, under normal operating conditions; said second circuit comprising means for comparing a ''''blank'''' calibrating signal at said first input to a second signal at said second input means and forming a second mathematical relationship therebetween; automatic recalibrating means associated with said second circuit for effectively changing at least one of said signals at one of said first and second input means by a third mathematical operation to cause said second mathematical relationship to attain a specific predetermined value; calibration memory means associated with said automatic recalibrating means for storing said third mathematical operation necessary to cause said second mathematical relationship to be maintained at said predetermined value; and means for performing said stored third mathematical operation on signals presented at at least said one input means during subsequent operations of said first computing circuit; whereby undesired error variations in the sources of said first and said second signals are eliminated from such subsequent computing operations of said first computing circuit means.
Claim 2
Dependent Claim
236 words
In a measuring circuit for determining a desired mathematical relationship between a first variable signal and a second signal, comprising: a first signal input means; a second signal input means; said first and second input means being common inputs to a first computing circuit and a second calibrating circuit; said first circuit comprising means for computing said desired mathematical relationship between said first and second signals applied to said first and second input means respectively, under normal operating conditions; said second circuit comprising means for comparing a ''''blank'''' calibrating signal at said first input to a second signal at said second input means and forming a second mathematical relationship therebetween; automatic recalibrating means associated with said second circuit for effectively changing at least one of said signals at one of said first and second input means by a third mathematical operation to cause said second mathematical relationship to attain a specific predetermined value; calibration memory means associated with said automatic recalibrating means for storing said third mathematical operation necessary to cause said second mathematical relationship to be maintained at said predetermined value; and means for performing said stored third mathematical operation on signals presented at at least said one input means during subsequent operations of said first computing circuit; whereby undesired error variations in the sources of said first and said second signals are eliminated from such subsequent computing operations of said first computing circuit means.
Claim 3
Dependent Claim
69 words
A measuring circuit according to claim 1, in which: a substantial part of each of said first computing and said second calibrating circuits comprises the same commonly shared components, so that said commonly shared components are utilized during both normal computing operations and during automatic calibration operations; whereby an appreciable reduction in the total combined number of components required for both said first and said second circuits is effected.
Claim 4
Dependent Claim
32 words
A measuring circuit according to claim 1, in which: said first computing circuit comprises an analog-to-digital converting means; whereby the results of said computed desired mathematical relationship are available in digital form.
Claim 5
Dependent Claim
75 words
A measuring circuit according to claim 3, in which: said second calibrating circuit comprises also said same analog-to-digital converting means; and said automatic recalibrating means associated with said second circuit is in such relative location as to receive said second mathematical relationship in already converted-to-digital form; whereby said third mathematical operation is performed in a digital manner so as to insure freedom from ''''drift'''' and other varying errors of components of said second calibrating circuit.
Claim 6
Dependent Claim
152 words
A measuring circuit according to claim 1, in which said first computing circuit comprises: means for temporarily storing a pair of signals having magnitudes at least proportional to each of said two input signals, respectively; means for forming a comparison ramp signal which continuously changes in amplitude according to a known mathematical curve; comparator means for determining when the amplitude of said changing comparison ramp signal is equal to each of said pair of stored signals; and means for measuring the elapsed time between when said comparator means determines such equality with said changing comparison ramp signal and each of said pair of stored signals; whereby said determined elapsed time is a particular mathematical relationship of the relative magnitudes of said pair of stored signals, and therefore of the values of the two input signals; said particular mathematical relationship being determined by said mathematical curve of said continuously changing comparison ramp signal.
Claim 7
Dependent Claim
53 words
A measuring circuit according to claim 5, in which: said comparison ramp signal forming means is of such construction as to at least optionally generate an exponentially changing ramp signal; whereby said measured elapsed time is a logarithmic function of the ratio of said two input signals, which is said desired mathematical relationship.
Claim 8
Dependent Claim
58 words
A measuring circuit according to claim 5, in which: said comparison ramp signal forming means is of such construction as to at least optionally generate a linearly changing ramp signal; whereby said measured elapsed time is at least directly proportional to the difference between the values of said two input signals, when this is said desired mathematical relationship.
Claim 9
Dependent Claim
41 words
A measuring circuit according to claim 5, in which: digital conversion means are Operatively connected to said elapsed time measuring means, to provide a number of digital pulses which number is directly proportional to the length of said measured elapsed time.
Claim 10
Dependent Claim
38 words
A measuring circuit according to claim 5, in which: analog readout means are operatively connected to said elapsed time measuring means, to provide an analog signal having an amplitude proportional to said length of said measured elapsed time.
Claim 11
Dependent Claim
152 words
A measuring circuit according to claim 1, in which said second calibrating circuit comprises: means for temporarily storing a pair of signals having magnitudes at least proportional to each of said two input signals, respectively; means for forming a comparison ramp signal which continuously changes in amplitude according to a known mathematical curve; comparator means for determining when the amplitude of said changing comparison ramp signal is equal to each of said pair of stored signals; and means for measuring the elapsed time between when said comparator means determines such equality with said changing comparison ramp signal and each of said pair of stored signals; whereby said determined elapsed time is a particular mathematical relationship of the relative magnitudes of said pair of stored signals, and therefore of the values of the two input signals; said particular mathematical relationship being determined by said mathematical curve of said continuously changing comparison ramp signal.
Claim 12
Dependent Claim
52 words
A measuring circuit according to claim 10, in which: said comparison ramp signal forming means is of such construction as to generate a linearly changing ramp signal; whereby said measured elapsed time is at least directly proportional to the difference of the said two input signals, which therefore is second mathematical relationship.
Claim 13
Dependent Claim
85 words
A measuring circuit according to claim 11, in which: said automatic recalibrating means comprises means for changing at least one of said input signals before said temporary storing means in such a manner as to cause said measured elapsed time to be reduced substantially to zero; thus causing said second mathematical relationship which is the difference in the changed calibrating input signals, to attain the specific predetermined value of zero by this third mathematical operation of effectively changing at least one of said input signals.
Claim 14
Dependent Claim
63 words
A measuring circuit according to claim 12, in which: the means accomplishing said third mathematical operation of changing at least one of said signals at said first and second input means comprises a variable signal attenuator for proportionally reducing the larger of the two original input signals until its proportionally reduced stored value equals the stored value of the other smaller input signal.
Claim 15
Dependent Claim
64 words
A measuring circuit according to claim 13, in which: said calibration memory means comprises means for storing that attenuator proportionality value which causes said larger input signal to be reduced to said smaller input signal; whereby during subsequent computing operations the signal supplied to said attenuated input means will be corrected in the same proportional manner by the same value of said signal attenuator.
Claim 16
Dependent Claim
71 words
A measuring circuit according to claim 13, in which: said signal attenuator comprises, at said larger signal input means, a chopping switch and means for supplying a repetitive, variable length ''''on'''' switching pulse to said chopping switch; said chopping switch therefore being a variable duty cycle ''''on'''' switch, causing effective attenuation of said larger input signal by a percentage factor if its ''''on'''' duty time relative to a complete switch cycle.
Claim 17
Dependent Claim
107 words
A measuring circuit according to claim 15, in which: said calibration memory means comprise a pair of continuously cycling memory signal generators, each generating a repetitive substantially identical signal; said automatic recalibrating means comprising means for adjusting the relative Phase of said pair of continuously cycling memory signal generators; means for sensing the relative phase difference of said memory signal generators and for varying said length of said repetitive ''''on'''' switching pulses in accordance with said sensed phase difference; whereby said automatic recalibrating means sets the phase difference of said continuously cycling memory signal generators, which phase difference subsequently determines the correcting attenuation during subsequent computing operations.
Claim 18
Dependent Claim
33 words
A measuring circuit according to claim 16, in which: said pair of continuously cycling memory signal generators are operatively driven by a common oscillatory input signal; whereby undesired relative phase slippages are avoided.
Claim 19
Dependent Claim
89 words
A measuring circuit according to claim 17, in which: said pair of continuously cycling memory signal generators comprise digital recycling counters, driven by a high frequency pulse clock; said relative phase difference sensing means comprises a flip-flop, the setting inputs of which are the output of the last stage of each said digital recycling counters, the output of said flip-flop therefore supplying the repetitive variable length ''''on'''' switching pulses to drive said chopping switch; whereby said calibration memory means comprises pulse-driven digital counters, immune to possible unintended phase changes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-17 | 1974-11-16 | 1975-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-17 | 1978-11-16 | 1979-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-17 | 1982-11-16 | 1983-05-18 | $7700.00 | Window Closed / Lapsed |