Multifunction logic network

Claim 2

A multifunction logic network for providing at an output terminal a signal representing a selected one of a plurality of functions of one, two and three variables represented by input signals present at data terminals in response to five control signals M1 to M5 applied to other terminals thereof comprising: first means for producing the ORed function of selected different ones of all possible AND functions of two of said variables A and D in response to said input signals representing said two variables, each AND function being selected by one of four of said control signals M1 to M4; and second means responsive to said first means and to control signal M5 for selectively translating to said first means and to control output terminal either a first output signal representing said ORed function of selected AND functions of two of said variables, or a second output signal representing said third variable ANDed with said ORed function of selected AND functions of two of said variables, or a third output signal representing the complement of said third variable ANDed with all of said AND functions of two of said variables not selected.

Claim 3

A logic network as defined in claim 1 wherein said third variable is the complement of a binary arithmetic carry for producing at said output terminal a signal representing the sum of said two variables and said carry when AND functions of said two variables are so selected that each variable is ANDed with the complement of the other, and said fifth control signal M5 selectively translates to said output terminal a signal representing the ANDed function of said third variable and the ORed function of each variable ANDed with the complement of the other, or the complement of said third variable and the ORed function of the AND function of said two variables and the complement of the AND function of said two variables.

Claim 4

A logic network as defined in claim 1 wherein said second means functions in response to said fifth control signal in accordance with the following Boolean logic equation: S (DAM1+DAM2+DAM3+DAM4)C+ (DAM1+DAM2+DAM3+DAM4)C where D, A and C are said variables.

Claim 5

A 2network as defined in claim 1 wherein said first means includes a first NOR gate connected to receive signals at input terminals thereof representing the functions DA, DA, DA, and DA selected for ORing by respective ones of said control signals M1, M2, M3 and M4, and inverting means coupling the output of said first gate to said network output terminal whereby a signal is produced at said output terminal representing the function: DAM1+DAM2+DAM3+DAM4

Claim 6

A logic network as defined in claim 4 wherein said second means comprises: a second NOR gate adapted to receive at input terminals thereof signals representing the functions DA, DA, DA and DA, selected for ORing in said first means by respective ones of said control signals M1, M2, M3 and M4; said third variable C; and the fifth one of said control signals M5 to thereby provide at an output terminal thereof a signal representing the following function: (DAM1+DAM2+DAM3+DAM4)CM5; the output terminal of said second gate being connected to a fifth input terminal of said first gate.

Claim 7

A logic network as defined in claim 5 wherein said inverting means comprises an output NOR gate having a second input terminal, and said second means further comprises a third NOR gate having its output terminal connected to said second input terminal of said output inverting logic gate, one input terminal connected to said output terminal of said second gate, one input terminal connected to receive said fifth control signal M5 and one input terminal connected to receive said third variable C, whereby a signal is produced at said network output terminal in accordance with the following Boolean logic equation: S (DAM1+DAM2+DAM3+DAM4)M5+ (DAM1+DAM2+DAM3+DAM4)CM5+ (DAM1+DAM2+DAM3+DAM4)CM5.

Claim 8

A multifunction logic network capable of providing 32 distinct operations in response to five signals from a control unit of which one operation is to selectively transmit a binary 0 signal, another is to selectively transmit a binary 1 signal, and 30 are to selectively transmit signals, each representing a function of one or more of three signals from a data source, each signal from the data source representing a variable, comprising: utilization means adapted to receive signals in response to desired ones of said 32 distinct operations; a first inverting gate having one output terminal connected to said utilization means and having two input terminals; second and third multiinput inverting gates, each having its output terminal connected to a different one of said input terminals of said first inverting gate; a fourth multiinput inverting gate having its output terminal connected to an input terminal of each of said second and third inverting gates; means connecting an input terminal of each of said third and fourth gates to said data source for receiving one variable; means connecting an input terminal of each of said third and fourth inverting gates to said control unit for receiving a predetermined one of said five control signals; means connected to said data source for receiving signals representing second and third variables and connected to said control unit for receiving the remaining four of five control signals, and in response to said second and third signals representing variables, and said remaining four control signals, producing selected ones of all possible AND functions of said second and third variables, each AND function being selected by one of the remaining four of said control signals; and means for coupling each one of said AND functions produced by said last-named means to a different input terminal of each of said second and fourth inverting gates.

Claim 9

A multifunction logic network capable of providing 32 distinct operations in response to five signals from a control unit of which one operation is to selectively transmit a binary 0 signal, another is to selectively transmit a binary 1 signal, and 30 are to selectively transmit signals, each representing a function of one or more of three signals from a data source, each signal from the data source representing a variable, comprising: utilization means adapted to receive signals in response to desired ones of said 32 distinct operations; a first inverting gate having one output terminal connected to said utilization means and having two input terminals; second and third multiinput inverting gates, each having its output terminal connected to a different one of said input terminals of said first inverting gate; a fourth multiinput inverting gate having its output terminal connected to an input terminal of each of said second and third inverting gates; means connecting an input terminal of each of said third and fourth gates to said data source for receiving one variable; means connecting an input terminal of each of said third and fourth inverting gates to said control unit for receiving a predetermined one of said five control signals; means connected to said data source for receiving signals representing second and third variables and connected to said control unit for receiving the remaining four of five control signals, and in response to said second and third signals representing variables, and said remaining four control signals, producing selected ones of all possible AND functions of said second and third variables, each AND function being selected by one of the remaining four of said control signals; and means for coupling each one of said AND functions produced by said last-named means to a different input terminal of each of said second and fourth inverting gates.

Claim 10

A multifunction logic network as defined in claim 7 wherein said means for producing the ORed function of selected ones of all possible AND functions of said second and third variables comprises four inverting logic gates and means for coupling input terminals of each of said four inverting gates to said data source for receiving at input terminals thereof all possible AND functions of said second and third signals, and complements thereof, and each of said four gates having one input terminal connected to a different one of said remaining four control signals.

Claim 11

A multifunction logic network as defined in claim 8 wherein each of said inverting gates consists of a direct-coupled transistor-logic gate consisting of field-effect transistors.

Claim 12

A multifunction logic network as defined in claim 9 wherein said field-effect transistors are insulated-gate field-effect transistors.

Claim 13

A logic network for providing a network output terminal a signal representing a selected one of a plurality of functions of one, two and three variables represented by input signals present at data terminals in response to five control signals M1 to M5 applied to other terminals comprising: gating means for producing at four separate terminals selected different ones of all possible AND functions of two variables A and D in response to four control signals M1 to M4; a first NOR gate having four input terminals connected to said four separate terminals of said gating means for producing at an output terminal thereof a complement of the ORed function of Selected ones of all possible AND functions of two variables produced by said first means; a second NOR gate having one input terminal connected to the output terminal of said first NOR gate and an output terminal connected to said network output terminal; a third NOR gate having four input terminals connected to said four separate terminals of said gating means, a fifth input terminal connected to receive said third variable and a sixth input terminal connected to receive said third variable and a sixth input terminal connected to receive said fifth control signal M5, and an output terminal connected to a fifth input terminal of said first NOR gate; and a fourth NOR gate having an input terminal connected to said third-gate output terminal, an input terminal connected to receive said fifth control signal, an input terminal connected to receive said third variable signal, and an output terminal connected to an input terminal of said second NOR gate.

Claim 14

A logic network for providing a network output terminal a signal representing a selected one of a plurality of functions of one, two and three variables represented by input signals present at data terminals in response to five control signals M1 to M5 applied to other terminals comprising: gating means for producing at four separate terminals selected different ones of all possible AND functions of two variables A and D in response to four control signals M1 to M4; a first NOR gate having four input terminals connected to said four separate terminals of said gating means for producing at an output terminal thereof a complement of the ORed function of Selected ones of all possible AND functions of two variables produced by said first means; a second NOR gate having one input terminal connected to the output terminal of said first NOR gate and an output terminal connected to said network output terminal; a third NOR gate having four input terminals connected to said four separate terminals of said gating means, a fifth input terminal connected to receive said third variable and a sixth input terminal connected to receive said third variable and a sixth input terminal connected to receive said fifth control signal M5, and an output terminal connected to a fifth input terminal of said first NOR gate; and a fourth NOR gate having an input terminal connected to said third-gate output terminal, an input terminal connected to receive said fifth control signal, an input terminal connected to receive said third variable signal, and an output terminal connected to an input terminal of said second NOR gate.

Claim 15

In combination: a source of signals representing five control signals M1 to M5; a source of signals representing two variables and complements thereof; a source of signals representing a third variable; a group of four NOR gates, each having three input terminals, one connected to receive a different one of four control signals M1 to M4 and two connected to receive pairs of signals, each pair representing a different one of four possible combinations of said two variables and complements thereof taken two at a time, except a combination of one of said two variables and its complement and a combination of the other of said two variables and its complement; a fifth NOR gate having each of four input terminals connected to an output terminal of a different one of said four NOR gates, a fifth input terminal of a different one of said four NOR gates, a fifth input terminal connected to receive said fifth control signal M5, and a sixth input terminal connected to receive signals representing said third variable; a sixth NOR gate having each of four input terminals connected to an output terminal of a different one of said four NOR gates, and a fifth input terminal connected to the output terminal of said fifth NOR gate; a seventh NOR gate having three input terminals, one connected to receive said fifth control signal, one connected to receive signals representing said third variable, and one connected to the output terminal of said fifth NOR gate; and an eighth NOR gate having two input terminals, each connected to a different one of the output terminals of said sixth and seventh NOR gates, and an output terminal.

Claim 16

In combination: a source of signals representing five control signals M1 to M5; a source of signals representing two variables and complements thereof; a source of signals representing a third variable; a group of four NOR gates, each having three input terminals, one connected to receive a different one of four control signals M1 to M4 and two connected to receive pairs of signals, each pair representing a different one of four possible combinations of said two variables and complements thereof taken two at a time, except a combination of one of said two variables and its complement and a combination of the other of said two variables and its complement; a fifth NOR gate having each of four input terminals connected to an output terminal of a different one of said four NOR gates, a fifth input terminal of a different one of said four NOR gates, a fifth input terminal connected to receive said fifth control signal M5, and a sixth input terminal connected to receive signals representing said third variable; a sixth NOR gate having each of four input terminals connected to an output terminal of a different one of said four NOR gates, and a fifth input terminal connected to the output terminal of said fifth NOR gate; a seventh NOR gate having three input terminals, one connected to receive said fifth control signal, one connected to receive signals representing said third variable, and one connected to the output terminal of said fifth NOR gate; and an eighth NOR gate having two input terminals, each connected to a different one of the output terminals of said sixth and seventh NOR gates, and an output terminal.

Claim 17

A digital logic network useful in an arithmetic unit for providing an output signal selectively representing the sum of three variables as well as a plurality of other functions of said three variables, said network including: a data source providing first, second, and third binary input signals respectively representing first, second and third variables of said three variables; a set of four gates; means for coupling said first and second input signals to said set of four gates to develop signals respectively representing different ones of the four possible AND functions of said first and second variables; a signal source providing at least five binary control signals; means applying each of four of said control signals to a different one of said four gates; and output gating means responsive to said fifth control signal, said third input signal, and said signals developed by said four gates for producing an output signal representing a particular function of said three variables determined by the states of said control signals.

Claim 18

A digital logic network useful in an arithmetic unit for providing an output signal selectively representing the sum of three variables as well as a plurality of other functions of said three variables, said network including: a data source providing first, second, and third binary input signals respectively representing first, second and third variables of said three variables; a set of four gates; means for coupling said first and second input signals to said set of four gates to develop signals respectively representing different ones of the four possible AND functions of said first and second variables; a signal source providing at least five binary control signals; means applying each of four of said control signals to a different one of said four gates; and output gating means responsive to said fifth control signal, said third input signal, and said signals developed by said four gates for producing an output signal representing a particular function of said three variables determined by the states of said control signals.