Memory with error correction for partial store operation

Claim 2

In combination with memory storing multibyte words of data in an error correction code and an associated system operating on words not in said code, the improvement comprising; register means for receiving a word read from said memory and for receiving marked bytes of a word from said associated system, any marked bytes from said associated system and any unmarked bytes from said memory constituting a word to be stored; first means connected to said register means to receive said word to be stored to form error correction bits for said word to be stored; second means connected to said register means to receive said word read from said memory and to correct errors in said memory word and to correct any corresponding error in an unmarked byte of said word to be stored; and and third means connected to be responsive to said second means to change the error correction code bits in said register means according to a corrected error.

Claim 3

The improvement of claim 1 in which said error correction bit forming means includes circuits to form error correction bits distinct from data bits in said word to be stored.

Claim 4

In combination with a memory storing multibyte data words in an error correction code and operating with an associated system supplying words or marked bytes of words not in said error correction code for store and partial store operations, the improvement comprising, store register means connected to receive marked data bytes from said associated system, and error correction encoding means connected to receive the word in said store register means and to provide to said store register means an error correction encoded word for storage in said memory; fetch register means connected to receive both marked and unmarked bytes from said memory, and means for correcting an error in said fetch register and in any corresponding unmarked byte in said store register means; and means responsive to said error-correcting means to update the error correction code in said store register means when a data correction is made in said store register.

Claim 5

In combination with a memory storing multibyte data words in an error correction code and operating with an associated system supplying words or marked bytes of words not in said error correction code for store and partial store operations, the improvement comprising, store register means connected to receive marked data bytes from said associated system, and error correction encoding means connected to receive the word in said store register means and to provide to said store register means an error correction encoded word for storage in said memory; fetch register means connected to receive both marked and unmarked bytes from said memory, and means for correcting an error in said fetch register and in any corresponding unmarked byte in said store register means; and means responsive to said error-correcting means to update the error correction code in said store register means when a data correction is made in said store register.

Claim 6

The improvement of claim 3 further including a parity generator connected to receive data in said fetch register means and to provide a parity bit for each byte, a register connected to receive said parity bits, and means responsive to said error correcting means to complement the stage of said parity register corresponding to the byte in which an error is located.

Claim 7

The improvement of claim 3 in which said error-correcting encoding means includes circuits to form error correction code bits distinct from data bits.

Claim 8

The improvement of claim 5 in which said error-correcting means includes an exclusive OR circuit forming syndrome bits according to the data and error correction code bits of said fetch register means, and further includes means for decoding said syndrome bits to locate any error bit position and to detect predetermined uncorrectable errors.

Claim 9

The improvement of claim 6 in which said means to update said error correction bits comprises logic circuits connected to said decoding means according to the relationship of data bits to error correction code bits in the error correction code.

Claim 10

The improvement of claim 6 in which said syndrome decoding means includes means providing intermediate outputs according to logical combinations of selected syndrome bits and other intermediate outputs according to logical combinations of other syndrome bits, and said update means includes means logically combining said intermediate outputs according to the relationship between said check bits and the bit error location defined by said intermediate outputs.

Claim 11

The improvement of claim 5 in which said error correction means includes means responsive to a correction code bit error to inhibit an erroneous correction to any of said registers.

Claim 12

The improvement of claim 5 in which said encoding circuit includes means providing a single error correcting and double error deTecting code and said error-correcting means includes means responsive to a single data bit error to perform an error correction and responsive to a double error to signal an uncorrectable error to said associated system, and to inhibit an invalid correction.