Pulse delay circuit

Claim 2

A pulse delay circuit for producing an output pulse a predetermined time after application of an input pulse comprising: a source providing an input pulse; a bistable device directly responsive to said input pulse to change its state and provide an output signal; circuit means also directly responsive to said input pulse to initiate the generation of a linearly varying signal with respect to time commencing when said input pulse is directly received by the circuit means and responsive to the output signal of said bistable device for continuing its generation thereafter; reference signal means providing a second signal having a constant reference potential; and comparing means for comparing said linearly varying signal and said second signal and providing a delayed output signal when the potential of said linearly varying signal exceeds said second signal whereby the time delay of said output signal is determined by the time required for said first signal to exceed said second signal.

Claim 3

A pulse delay circuit for producing an output pulse a predetermined time after application of an input pulse comprising: a source providing an input pulse; a bistable device directly responsive to said input pulse to change its state and provide an output signal; circuit means also directly responsive to said input pulse to initiate the generation of a linearly varying signal with respect to time commencing when said input pulse is directly received by the circuit means and responsive to the output signal of said bistable device for continuing its generation thereafter; reference signal means providing a second signal having a constant reference potential; comparing means for comparing said linearly varying signal and said second signal and providing a delayed output signal when the potential of said linearly varying signal exceeds said second signal whereby the time delay of said output signal is determined by the time required for said first signal to exceed said second signal; and reset means responsive to said delayed output signal for restoring said bistable device to its original state and thus preparing the pulse delay circuit for receipt of a second input pulse.

Claim 4

A pulse delay circuit for producing an output pulse a predetermined time after application of an input pulse comprising: a source providing an input pulse; a bistable device directly responsive to said input pulse to change its state and provide an output signal; circuit means also directly responsive to said input pulse to initiate the generation of a linearly varying signal with respect to time commencing when said input pulse is directly received by the circuit means and responsive to the output signal of said bistable device for continuing its generation thereafter; reference signal means providing a second signal having a constant reference potential; comparing means for comparing said linearly varying signal and said second signal and providing a delayed output signal when the potential of said linearly varying signal exceeds said second signal whereby the time delay of said output signal is determined by the time required for said first signal to exceed said second signal; and reset means responsive to said delayed output signal for restoring said bistable device to its original state and thus preparing the pulse delay circuit for receipt of a second input pulse.

Claim 5

A pulse delay circuit for producing an output pulse a predetermined time after application of an input pulse comprising: a source providing an input pulse; a bistable device directly responsive to said input pulse to change its state and provide an output signAl; circuit means also directly responsive to said input pulse to initiate the generation of a linearly varying signal with respect to time commencing when said input pulse is directly received by the circuit means and responsive to the output signal of said bistable device for continuing its generation thereafter; reference signal means providing a second signal having a constant reference potential; a common power supply for both said circuit means and said reference signal means whereby voltage variations in said power supply have no effect on time delay; comparing means for comparing said linearly varying signal and said second signal and providing a delayed output signal when the potential of said linearly varying signal exceeds said second signal whereby the time delay of said output signal is determined by the time required for said first signal to exceed said second signal; and reset means responsive to said delayed output signal for restoring said bistable device to its original state and thus preparing the pulse delay circuit for receipt of a second input pulse.

Claim 6

A pulse delay circuit for producing an output pulse a predetermined time after application of an input pulse comprising: a source providing an input pulse; a bistable device directly responsive to said input pulse to change its state and provide an output signAl; circuit means also directly responsive to said input pulse to initiate the generation of a linearly varying signal with respect to time commencing when said input pulse is directly received by the circuit means and responsive to the output signal of said bistable device for continuing its generation thereafter; reference signal means providing a second signal having a constant reference potential; a common power supply for both said circuit means and said reference signal means whereby voltage variations in said power supply have no effect on time delay; comparing means for comparing said linearly varying signal and said second signal and providing a delayed output signal when the potential of said linearly varying signal exceeds said second signal whereby the time delay of said output signal is determined by the time required for said first signal to exceed said second signal; and reset means responsive to said delayed output signal for restoring said bistable device to its original state and thus preparing the pulse delay circuit for receipt of a second input pulse.

Claim 7

A pulse delay circuit comprising: a source providing an input pulse; a bistable multivibrator providing an output signal in response to said input signals thereto, said multivibrator including: an output lead; a first input directly responsive to an input trigger pulse for switching said multivibrator from a first state to a second state wherein a high potential output signal is transmitted therefrom in said second state; a second input responsive to a reset pulse for switching said multivibrator from said second state to said first state wherein a low potential output signal is transmitted therefrom in said first state; a differential amplifier providing a positive output pulse when the potential of a signal to a first input of said amplifier exceeds the potential of a signal to a second input thereof; reference signal means connected to the second input of said amplifier providing a reference potential signal thereto; circuit means between said multivibrator output and the first input of said amplifier and directly receiving said input trigger pulse to initiate a linearly varying signal with respect to time to said amplifier and to continue its generation in response to said multivibrator high potential output signal, whereby the continuing signal on the first input of said amplifier is dependent on the state of said multivibrator and the time delay of said output pulse is determined by the time required for said linearly varying signal to exceed said reference signal; and means for applying the output pulse from said differential amplifier to the second input of said multivibrator to reset the delay circuit for the next operation.

Claim 8

A pulse delay circuit comprising: a source providing an input pulse; a bistable multivibrator providing an output signal in response to said input signals thereto, said multivibrator including: an output lead; a first input directly responsive to an input trigger pulse for switching said multivibrator from a first state to a second state wherein a high potential output signal is transmitted therefrom in said second state; a second input responsive to a reset pulse for switching said multivibrator from said second state to said first state wherein a low potential output signal is transmitted therefrom in said first state; a differential amplifier providing a positive output pulse when the potential of a signal to a first input of said amplifier exceeds the potential of a signal to a second input thereof; reference signal means connected to the second input of said amplifier providing a reference potential signal thereto; circuit means between said multivibrator output and the first input of said amplifier and directly receiving said input trigger pulse to initiate a linearly varying signal with respect to time to said amplifier and to continue its generation in response to said multivibrator high potential output signal, whereby the continuing signal on the first input of said amplifier is dependent on the state of said multivibrator and the time delay of said output pulse is determined by the time required for said linearly varying signal to exceed said reference signal; and means for applying the output pulse from said differential amplifier to the second input of said multivibrator to reset the delay circuit for the next operation.

Claim 9

A pulse delay circuit as set forth in claim 4 in which said circuit means further comprises a resistor and capacitor network operable between a positive power supply and ground to provide a relatively linearly increasing potential across said capacitor with respect to time, said network being connectable at a point between said resistor and capacitor to said circuit means between the first output of said amplifier and said multivibrator output whereby when the potential across said capacitor and applied to said amplifier first input exceeds the potential on said amplifier second input a positive pulse is transmitted from said differential amplifier and the time delay of said pulse delay circuit is governed by the value of said capacitor, the charging current through said resistor and the peak potential that said capacitor will reach.

Claim 10

A pulse delay circuit as set forth in claim 5 further comprising: enabling means connected in said circuit means between said multivibrator output and said network connection point for disabling current flow in said circuit means between said multivibrator output and said network connection in response to said multivibrator second state output signal and for enablinG current flow in response to said input pulse and to said multivibrator first state output signal; a reset line connecting said differential amplifier output and said multivibrator second input whereby said amplifier output pulse provides the reset pulse for switching said multivibrator to its first state thereby enabling said enabling means for current flow therethrough whereby the level of said amplifier first input signal becomes less than said reference level signal and thereby prevents further transmission of amplifier positive output pulses; and discharge means providing a discharge path for said capacitor when said multivibrator output switches to the first state.

Claim 11

A pulse delay circuit comprising: a source providing an input pulse; a bistable multivibrator providing an output signal in response to said input signals thereto, said multivibrator including: an output lead; a first input directly responsive to an input trigger pulse for switching said multivibrator from a first state to a second state wherein a high potential output signal is transmitted therefrom in said second state; and a second input responsive to a reset pulse for switching said multivibrator from said second state to said first state wherein a low potential output signal is transmitted therefrom in said first state; a differential amplifier providing a positive output pulse when the potential of a signal to a first input of said amplifier exceeds the potential of a signal to a second input thereof; reference signal means connected to the second input of said amplifier providing a reference potential signal thereto; circuit means between said multivibrator output and the first input of said amplifier and directly receiving said input trigger pulse to initiate a linearly varying signal with respect to time to said amplifier and to continue its generation in response to said multivibrator high potential output signal, whereby the continuing signal on the first input of said amplifier is dependent on the state of said multivibrator and the time delay of said output pulse is determined by the time required for said linearly varying signal to exceed said reference signal; means for applying the output pulse from said differential amplifier to the second input of said multivibrator to reset the delay circuit for the next operation; and a common power supply for both the second input of said differential amplifier and for said reference signal means whereby voltage variations in said power supply have no effect on time delay.

Claim 12

A pulse delay circuit comprising: a source providing an input pulse; a bistable multivibrator providing an output signal in response to said input signals thereto, said multivibrator including: an output lead; a first input directly responsive to an input trigger pulse for switching said multivibrator from a first state to a second state wherein a high potential output signal is transmitted therefrom in said second state; and a second input responsive to a reset pulse for switching said multivibrator from said second state to said first state wherein a low potential output signal is transmitted therefrom in said first state; a differential amplifier providing a positive output pulse when the potential of a signal to a first input of said amplifier exceeds the potential of a signal to a second input thereof; reference signal means connected to the second input of said amplifier providing a reference potential signal thereto; circuit means between said multivibrator output and the first input of said amplifier and directly receiving said input trigger pulse to initiate a linearly varying signal with respect to time to said amplifier and to continue its generation in response to said multivibrator high potential output signal, whereby the continuing signal on the first input of said amplifier is dependent on the state of said multivibrator and the time delay of said output pulse is determined by the time required for said linearly varying signal to exceed said reference signal; means for applying the output pulse from said differential amplifier to the second input of said multivibrator to reset the delay circuit for the next operation; and a common power supply for both the second input of said differential amplifier and for said reference signal means whereby voltage variations in said power supply have no effect on time delay.