Data readout system

Claim 2

In a system for making differential measurements based on successive measurement periods, the combination of: means for producing a pulse train in which the number of pulses for a determined period is representative of the measurement during one of the measurement periods; bidirectional counter means for counting the pulses during the determined period; control means for the counter means for operating the counter in the proper direction to perform the algebraic function between successive measurement periods necessary to provide the desired differential measurement; comparator means connected to the counter for comparing the data represented by the count of the counter with a programmed limit number and producing a logic signal representative of the relative value of the two numbers, the comparator means comprising a plurality of comparator stages each comprised of first gate means for producing the logic product of the true data bit value and the complement limit bit value at its output and second gate means for producing the logic product of the complement data bit value and the true limit bit value at its output; fourth logic means connected to the outputs of the second gate means of each stage for producing a first logic level indicative of one decision other than an ''''equal'''' decision at any stage and a second logic level indicative of a decision other than said one decision; fifth logic means interconnecting an output at each stage and an input of the second gate means of each lower order stage for disabling the lower order stage when a decision other than an ''''equal'''' decision or said one decision is reached at the stage; sixth logic means connected to the outputs of the second gate means at each stage for producing a first logic level when an ''''equal'''' decision is reached at all stages and a second logic level when other than an ''''equal'''' decision is reached at any stage; and seventh logic means connected to the output of the forth logic means and to an input of the sixth logic means for disabling the sixth logic means by producing said second logic level at its output when the output of the fourth logic means is at said first logic level.

Claim 3

a ''''forward'''' logic level and a ''''not reverse'''' logic level during a ''''count'''' logic level and during, a. a ''''zero'''' logic level at the third logic means; b. an ''''add'''' logic level at the fourth logic means and a ''''positive'''' logic level at the sixth logic means; or c. a ''''substract'''' logic level at the fourth logic means and a ''''negative'''' logic level at the sixth logic means; and

Claim 4

a ''''forward'''' logic level and a ''''not reverse'''' logic level during a ''''count'''' logic level and during, a. a ''''zero'''' logic level at the third logic means; b. an ''''add'''' logic level at the fourth logic means and a ''''positive'''' logic level at the sixth logic means; or c. a ''''substract'''' logic level at the fourth logic means and a ''''negative'''' logic level at the sixth logic means; and

Claim 5

The combination of defined in claim 1 wherein: the combination defined in claim 1 is a decade in which the outputs of the fourth and sixth logic means are the outputs of the decade and there are a plurality of such decades; eighth logic means connecting the outputs of the sixth logic means of each decade to the sixth logic means of the next lower order decade to enable the sixth logic means of the next lower order decade when the output of the sixth logic means of the higher order decade is at said first logic level indicative of an ''''equal'''' decision at all bits of the decade, and for disabling the sixth logic means of the next lower order decade if other than an ''''equal'''' decision is reached in the higher order decade; ninth logic means connected to the output of the fourth logic means of each decade for producing a logic level indicative of said one decision when said one decision is reached at a decade and an ''''equal'''' decision is reached at all higher order decades; and tenth logic means connected to the output of the sixth logic means of the lowest order decade for producing a logic level indicative of an ''''equal'''' decision when an ''''equal'''' decision is reached at all decades.

Claim 6

a ''''forward'''' logic level and a ''''not reverse'''' logic level during a ''''count'''' logic level and during a. a ''''zero'''' logic level at the third logic means; b. an ''''add'''' logic level at the fourth logic means and a ''''positive'''' logic level at the sixth logic means; or c. a ''''substract'''' logic level at the fourth logic means and a ''''negative'''' logic level at the sixth logic means; and

Claim 7

a ''''forward'''' logic level and a ''''not reverse'''' logic level during a ''''count'''' logic level and during a. a ''''zero'''' logic level at the third logic means; b. an ''''add'''' logic level at the fourth logic means and a ''''positive'''' logic level at the sixth logic means; or c. a ''''substract'''' logic level at the fourth logic means and a ''''negative'''' logic level at the sixth logic means; and

Claim 8

a ''''forward'''' logic level and a ''''not reverse'''' logic level during a ''''count'''' logic level and during: a. a ''''zero'''' logic level at the third logic means; b. an ''''add'''' logic level at the fourth logic means and a ''''positive'''' logic level at the sixth logic means; or c. a ''''substract'''' logic level at the fourth logic means and a ''''negative'''' logic level at the sixth logic means; and

Claim 9

a ''''forward'''' logic level and a ''''not reverse'''' logic level during a ''''count'''' logic level and during: a. a ''''zero'''' logic level at the third logic means; b. an ''''add'''' logic level at the fourth logic means and a ''''positive'''' logic level at the sixth logic means; or c. a ''''substract'''' logic level at the fourth logic means and a ''''negative'''' logic level at the sixth logic means; and

Claim 10

a ''''not forward'''' logic level and a ''''reverse'''' logic level during a ''''count'''' logic level at the fifth logic means; and a. a ''''not zero'''' logic level at the third logic means and a ''''substract'''' logic level at the fourth logic means and a ''''positive'''' logic level at the sixth logic means; or b. a ''''not zero'''' logic level at the third logic means and an ''''add'''' logic level at the fourth logic means, and a ''''negative'''' logic level at the sixth logic means.

Claim 11

a ''''not forward'''' logic level and a ''''reverse'''' logic level during a ''''count'''' logic level at the fifth logic means; and a. a ''''not zero'''' logic level at the third logic means and a ''''substract'''' logic level at the fourth logic means and a ''''positive'''' logic level at the sixth logic means; or b. a ''''not zero'''' logic level at the third logic means and an ''''add'''' logic level at the fourth logic means, and a ''''negative'''' logic level at the sixth logic means.

Claim 12

a ''''not forward'''' logic level and a ''''reverse'''' logic level during a ''''count'''' logic level at the fifth logic means; and a. a ''''not zero'''' logic level at the third logic means and a ''''substract'''' logic level at the fourth logic means and a ''''positive'''' logic level at the sixth logic means; or b. a ''''not zero'''' logic level at the third logic means and an ''''add'''' logic level at the fourth logic le means, and a ''''negative'''' logic level at the sixth logic means.

Claim 13

a ''''not forward'''' logic level and a ''''reverse'''' logic level during a ''''count'''' logic level at the fifth logic means; and a. a ''''not zero'''' logic level at the third logic means and a ''''substract'''' logic level at the fourth logic means and a ''''positive'''' logic level at the sixth logic means; or b. a ''''not zero'''' logic level at the third logic means and an ''''add'''' logic level at the fourth logic le means, and a ''''negative'''' logic level at the sixth logic means.

Claim 14

The combination defined in claim 2 further characterized by: eleventh logic means connected to the outputs of the ninth and tenth logic means for producing a logic level indicative of said other decision when the ninth logic means does not indicated indicate said one decision and tenth logic means does not indicate an ''''equal'''' decision.

Claim 15

a ''''not forward'''' logic level and a ''''reverse'''' logic level during a ''''count'''' logic level at the fifth logic means; and a. a ''''not zero'''' logic level at the third logic means and a ''''substract'''' logic level at the fourth logic means and a ''''positive'''' logic level at the sixth logic means; or b. a ''''not zero'''' logic level at the third logic means and an ''''add'''' logic level at the fourth logic means, and a ''''negative'''' logic level at the sixth logic means; and control means for the counter means for operating the counter in the proper direction to preform the algebraic functIon between successive measurement periods necessary to provide the desired differential measurement.

Claim 16

a ''''not forward'''' logic level and a ''''reverse'''' logic level during a ''''count'''' logic level at the fifth logic means; and a. a ''''not zero'''' logic level at the third logic means and a ''''substract'''' logic level at the fourth logic means and a ''''positive'''' logic level at the sixth logic means; or b. a ''''not zero'''' logic level at the third logic means and an ''''add'''' logic level at the fourth logic means, and a ''''negative'''' logic level at the sixth logic means; and control means for the counter means for operating the counter in the proper direction to preform the algebraic functIon between successive measurement periods necessary to provide the desired differential measurement.

Claim 17

The combination defined in claim 3 wherein one of the bits of the data and limit numbers represents the sign and further characterized by: logic means connected to the ninth and eleventh logic means for complementing the logic levels of the outputs of the ninth and tenth logic means when the signs of both the data number and limit number are negative and a decision other than ''''equal'''' is reached by the comparator.

Claim 18

In a system for making differential measurements based on successive measurement periods, the combination of: means for producing a pulse train in which the number of pulses for a determined period is representative of the measurement during one of the measurement periods; bidirectional counter means for counting the pulses during the determined period, the counter means comprising; a count forward input having ''''forward'''' and ''''not forward'''' logic levels, a count in reverse input having ''''reverse'''' and ''''not reverse'''' logic levels, and a plurality of binary stages each having a clock input, first and second input means, a complement mode when the ''''forward'''' and ''''not reverse'''' logic levels are applied to the first and second input means, respectively, a complement mode when the ''''not forward'''' and ''''reverse'''' logic levels are applied to the first and second input means, respectively, and a noncomplement mode when ''''not forward'''' and ''''not reverse'''' logic levels are applied to the first and second input means, respectively; clock means connected to continuously apply the pulses of a clock pulse train to the clock inputs of the binary stages; first logic means for applying the ''''forward'''' logic level at the count forward input to the first input means of the binary stages in a sequence to cause the binary stages to complement on successive clock pulses in a predetermined sequence to count forward and for continuously applying the ''''not reverse'''' logic level to the second input means of all binaries; second logic means for applying the ''''reverse'''' logic level of the count in reverse input to the second input means of the binary stages in a sequence to cause the binary stages to complement on successive clock pulses in a predetermined sequence to count in reverse and for continuously applying the ''''not reverse'''' logic level to the second inputs of all binaries; third logic means connected to the counter for producing a ''''zero'''' logic level when the counter is at the count of zero and a ''''not zero'''' logic level when the counter is at any other count; fourth logic means for producing an ''''add'''' logic level and a ''''substract'''' logic level in response to input control signals; fifth logic means for producing a ''''count'''' logic level and a ''''not count'''' logic level in response to the count signal; sixth logic means for producing a ''''positive'''' logic level when the data represented by the count of the counter is positive and a ''''negative'''' logic level when the data represented by the count of the counter is negative; seventh logic means connected to the outputs of the third, fourth, fifth and sixth logic means for producing at the respective forward and reverse inputs;

Claim 19

In a system for making differential measurements based on successive measurement periods, the combination of: means for producing a pulse train in which the number of pulses for a determined period is representative of the measurement during one of the measurement periods; bidirectional counter means for counting the pulses during the determined period, the counter means comprising; a count forward input having ''''forward'''' and ''''not forward'''' logic levels, a count in reverse input having ''''reverse'''' and ''''not reverse'''' logic levels, and a plurality of binary stages each having a clock input, first and second input means, a complement mode when the ''''forward'''' and ''''not reverse'''' logic levels are applied to the first and second input means, respectively, a complement mode when the ''''not forward'''' and ''''reverse'''' logic levels are applied to the first and second input means, respectively, and a noncomplement mode when ''''not forward'''' and ''''not reverse'''' logic levels are applied to the first and second input means, respectively; clock means connected to continuously apply the pulses of a clock pulse train to the clock inputs of the binary stages; first logic means for applying the ''''forward'''' logic level at the count forward input to the first input means of the binary stages in a sequence to cause the binary stages to complement on successive clock pulses in a predetermined sequence to count forward and for continuously applying the ''''not reverse'''' logic level to the second input means of all binaries; second logic means for applying the ''''reverse'''' logic level of the count in reverse input to the second input means of the binary stages in a sequence to cause the binary stages to complement on successive clock pulses in a predetermined sequence to count in reverse and for continuously applying the ''''not reverse'''' logic level to the second inputs of all binaries; third logic means connected to the counter for producing a ''''zero'''' logic level when the counter is at the count of zero and a ''''not zero'''' logic level when the counter is at any other count; fourth logic means for producing an ''''add'''' logic level and a ''''substract'''' logic level in response to input control signals; fifth logic means for producing a ''''count'''' logic level and a ''''not count'''' logic level in response to the count signal; sixth logic means for producing a ''''positive'''' logic level when the data represented by the count of the counter is positive and a ''''negative'''' logic level when the data represented by the count of the counter is negative; seventh logic means connected to the outputs of the third, fourth, fifth and sixth logic means for producing at the respective forward and reverse inputs;

Claim 20

The combination defined in claim 5 wherein the fifth logic means includes: a second counter comprised of a plurality of binary stages interconnected by eight logic means for successively complementing to a logic 1 state on successive clock pulses applied to the counter after the first binary stage complements to a logic 1 state, the output of the first binary stage being the output of the fifth logic means; ninth programmable logic means interconnecting the outputs of the binary stage of the second counter and the inputs of the first binary stage of the second counter for complementing the first binary stage to a logic 1 state after a selected binary stage has complemented to a logic 1 state; and tenth logic means connected to disable the eighth logic means and the output of the first binary stage in the absence of an enabling control signal.

Claim 21

The combination defined in claim 6 wherein fifth the fifth logic means further includes: logic means for selectively, by a programmed control signal, producing a count signal having a duration representative of the data value to be measured or, in the alternative, for producing a count signal of a predetermined reference period; and logic means for selectively, by said programmed control signals, gating through a constant frequency clock pulse train to the counter or, in the alternative, for gating through a clock pulse train having a modulated frequency representative of the data value to be measured.

Claim 22

The combination defined in claim 7 wherein the logic means for producing a count signal of a predetermined reference period is comprised of: counter means for counting a predetermined number of pulses of a constant frequency clock pulse train to produce a first logic signal having a duration equal to said predetermined number of clock pulses; and synchronous logic means operated in synchronism with the modulated frequency clock pulse train for producing a second logic signal for controlling said counter, said second logic signal starting on the first clock pulse of the modulated frequency clock pulse train after the start of the first logic signal and terminating on the first clock pulse of the modulated frequency clock pulse train after the termination of the first logic signal.

Claim 23

In a counter for a data readout system, the combination of: a count forward input having ''''forward'''' and ''''not forward'''' logic levels; a count in reverse input having ''''reverse'''' and ''''not reverse'''' logic levels; a plurality of binary stages each having a clock input, first and second input means, a complement mode when the ''''forward'''' and ''''not reverse'''' logic levels are applied to the first and second input means, respectively, a complement mode when the ''''not forward'''' and ''''reverse'''' logic levels are applied to the first and second input means, respectively, and a noncomplement mode when ''''not forward'''' and ''''not reverse'''' logic levels are applied to the first and second input means, respectively; clock means connected to continuously apply the pulses of a clock pulse train to the clock inputs of the binary stages; first logic means for applying the ''''forward'''' logic level at the count forward input to the first input means of the binary stages in a sequence to cause the binary stages to complement on successive clock pulses in a predetermined sequence to count forward and for applying the ''''not forward'''' logic level to the first input means of all binaries; and second logic means for applying the ''''reverse'''' logic level of the count in reverse input to the second input means of the binary stages in a sequence to cause the binary stages to complement on successive clock pulses in a predetermined sequence to count in reverse and for applying the ''''not reverse'''' logic level tot tO the second inputs of all binaries.

Claim 24

In a counter for a data readout system, the combination of: a count forward input having ''''forward'''' and ''''not forward'''' logic levels; a count in reverse input having ''''reverse'''' and ''''not reverse'''' logic levels; a plurality of binary stages each having a clock input, first and second input means, a complement mode when the ''''forward'''' and ''''not reverse'''' logic levels are applied to the first and second input means, respectively, a complement mode when the ''''not forward'''' and ''''reverse'''' logic levels are applied to the first and second input means, respectively, and a noncomplement mode when ''''not forward'''' and ''''not reverse'''' logic levels are applied to the first and second input means, respectively; clock means connected to continuously apply the pulses of a clock pulse train to the clock inputs of the binary stages; first logic means for applying the ''''forward'''' logic level at the count forward input to the first input means of the binary stages in a sequence to cause the binary stages to complement on successive clock pulses in a predetermined sequence to count forward and for applying the ''''not forward'''' logic level to the first input means of all binaries; and second logic means for applying the ''''reverse'''' logic level of the count in reverse input to the second input means of the binary stages in a sequence to cause the binary stages to complement on successive clock pulses in a predetermined sequence to count in reverse and for applying the ''''not reverse'''' logic level tot tO the second inputs of all binaries.

Claim 25

The combination defined in claim 9 wherein: the binary stages are J-K flip-flops, the J* and K* inputs are one input means, and the J and K inputs are the other input means.

Claim 26

The combination defined in claim 9 wherein there are four binary stages forming a decade for counting forward from zero to nine and resetting to zero and for counting in reverse from zero to one and resetting to zero.

Claim 27

The combination defined in claim 11 wherein the binary stages count in a 1:2:4:8 code.

Claim 28

The combination defined in claim 12 wherein there are a plurality of cascaded decades.

Claim 29

In a counter for a data readout system, the combination of: a count forward input having ''''forward'''' and ''''not forward'''' logic levels; a count in reverse input having ''''reverse'''' and ''''not reverse'''' logic levels; a plurality of binary stages each having a clock input, first and second input means, a complement mode when the ''''forward'''' and ''''not reverse'''' logic levels are applied to the first and second input means, respectively, a complement mode when the ''''not forward'''' and ''''reverse'''' logic levels are applied to the first and second input means, respectively, and a noncomplement mode when ''''not forward'''' and ''''not reverse'''' logic levels are applied to the first and second input means, respectively; clock means connected to continuously apply the pulses of a clock pulse train to the clock inputs of the binary stages; first logic means for applying the ''''forward'''' logic level at the count forward input to the first input means of the binary stages in a sequence to cause the binary stages to complement on successive clock pulses in a predetermined sequence to count forward and for continuously applying the ''''not reverse'''' logic level to the second input means of all binaries; second logic means for applying the ''''reverse'''' logic level of the count in reverse input to the second input means of the binary stages in a sequence to cause the binary stages to complement on successive clock pulses in a predetermined sequence to count in reverse and for continuously applying the ''''not reverse'''' logic level to the second inputs of all binaries; third logic means connected to the counter for producing a ''''zero'''' logic level when the counter is at the count of zero and a ''''not zero'''' logic level when the counter is at any other count; fourth logic means for producing an ''''add'''' logic level and a ''''substract'''' logic level in response to input control signals; fifth logic means for producing a ''''count'''' logic level and a ''''not count'''' logic level in response to an input control signal; sixth logic means for producing a ''''positive'''' logic level when the data represented by the count of the counter is positive and a ''''negative'''' logic level when the data represented by the count of the counter is negative; seventh logic le means connected to the outputs of the third, fourth, fifth and sixth logic means for producing at the respective forward and reverse inputs;

Claim 30

In a counter for a data readout system, the combination of: a count forward input having ''''forward'''' and ''''not forward'''' logic levels; a count in reverse input having ''''reverse'''' and ''''not reverse'''' logic levels; a plurality of binary stages each having a clock input, first and second input means, a complement mode when the ''''forward'''' and ''''not reverse'''' logic levels are applied to the first and second input means, respectively, a complement mode when the ''''not forward'''' and ''''reverse'''' logic levels are applied to the first and second input means, respectively, and a noncomplement mode when ''''not forward'''' and ''''not reverse'''' logic levels are applied to the first and second input means, respectively; clock means connected to continuously apply the pulses of a clock pulse train to the clock inputs of the binary stages; first logic means for applying the ''''forward'''' logic level at the count forward input to the first input means of the binary stages in a sequence to cause the binary stages to complement on successive clock pulses in a predetermined sequence to count forward and for continuously applying the ''''not reverse'''' logic level to the second input means of all binaries; second logic means for applying the ''''reverse'''' logic level of the count in reverse input to the second input means of the binary stages in a sequence to cause the binary stages to complement on successive clock pulses in a predetermined sequence to count in reverse and for continuously applying the ''''not reverse'''' logic level to the second inputs of all binaries; third logic means connected to the counter for producing a ''''zero'''' logic level when the counter is at the count of zero and a ''''not zero'''' logic level when the counter is at any other count; fourth logic means for producing an ''''add'''' logic level and a ''''substract'''' logic level in response to input control signals; fifth logic means for producing a ''''count'''' logic level and a ''''not count'''' logic level in response to an input control signal; sixth logic means for producing a ''''positive'''' logic level when the data represented by the count of the counter is positive and a ''''negative'''' logic level when the data represented by the count of the counter is negative; seventh logic le means connected to the outputs of the third, fourth, fifth and sixth logic means for producing at the respective forward and reverse inputs;

Claim 31

The combination defined in claim 14 wherein the fifth logic means comprises: a second counter comprised of a plurality of binary stages interconnected by eight logic means for successively complementing to a logic 1 state on successive clock pulses applied to the counter after the first binary stage complements to a logic 1 state, the output of the first binary stage being the output of the fifth logic means; ninth programmable logic means interconnecting the outputs of the binary stage of the second counter and the inputs of the first binary stage of the second counter for complementing the first binary stage to a logic 1 state after a selected binary stage has complemented to a logic 1 state; and tenth logic means connected to disable the eighth logic means and the output of the first binary stage in the absence of an enabling control signal.

Claim 32

In a digital data readout system, the combination of: a bidirectional synchronous counter having forward and reverse inputs for counting forward when a ''''forward'''' logic level is on the forward input and a ''''not forward'''' logic level on the reverse input, for counting in reverse when a ''''not forward'''' logic level is on the forward input and a ''''reverse'''' logic level is on the reverse input, and for not counting when a ''''not forward'''' logic level is on the forward input and a ''''not reverse'''' logic level is on the reverse input; third logic means connected to the counter for producing a ''''zero'''' logic level when the counter is at the count of zero and a ''''not zero'''' logic level when the counter is at any other count; fourth logic means for producing an ''''add'''' logic level and a ''''substract'''' logic level in response to input control signals; fifth logic means for producing a ''''count'''' logic level and a ''''not count'''' logic level in response to an input control signal; sixth logic means for producing a ''''positive'''' logic level when the data represented by the count of the counter is positive and a ''''negative'''' logic level when the data represented by the count of the counter is negative; seventh logic means connected to the outputs of the third, fourth, fifth and sixth logic means for producing at the respective forward and reverse inputs;

Claim 33

In a digital data readout system, the combination of: a bidirectional synchronous counter having forward and reverse inputs for counting forward when a ''''forward'''' logic level is on the forward input and a ''''not forward'''' logic level on the reverse input, for counting in reverse when a ''''not forward'''' logic level is on the forward input and a ''''reverse'''' logic level is on the reverse input, and for not counting when a ''''not forward'''' logic level is on the forward input and a ''''not reverse'''' logic level is on the reverse input; third logic means connected to the counter for producing a ''''zero'''' logic level when the counter is at the count of zero and a ''''not zero'''' logic level when the counter is at any other count; fourth logic means for producing an ''''add'''' logic level and a ''''substract'''' logic level in response to input control signals; fifth logic means for producing a ''''count'''' logic level and a ''''not count'''' logic level in response to an input control signal; sixth logic means for producing a ''''positive'''' logic level when the data represented by the count of the counter is positive and a ''''negative'''' logic level when the data represented by the count of the counter is negative; seventh logic means connected to the outputs of the third, fourth, fifth and sixth logic means for producing at the respective forward and reverse inputs;

Claim 34

The combination defined in claim 16 wherein the fifth logic means comprises: a second counter comprised of a plurality of binary stages interconnectEd by eighth logic means for successively complementing to a logic 1 state on successive clock pulses applied to the counter after the first binary stage complements to a logic 1 state, the output of the first binary stage being the output of the fifth logic means; ninth programmable logic means interconnecting the outputs of the binary a stage of the second counter and the inputs of the first binary stage of the second counter for complementing the first binary stage to a logic 1 state after a selected binary stage has complemented to a logic 1 state; and tenth logic means connected to disable the eighth logic means and the output of the first binary stage in the absence of an enabling control signal.

Claim 35

In a digital comparator for comparing a multibit binary data number with a binary limit number having an equal number of bits, the combination of: a plurality of comparator stages each comprised of first gate means for producing the logic product of the true data bit value and the complement limit bit value at its output, and second gate means for producing the logic product of the complement data bit value and the true limit bit value at its output; third gate logic means for producing an ''''equal'''' logic condition when the outputs at each comparator stage are at the same logic level, a ''''greater than'''' logic condition when the output of the first gate means of the highest order stage at which the outputs of the first and second gate means are not the same logic level is at a first logic level and the output of the second gate means is at a second logic level, and a ''''less than'''' logic condition when the output of the first gate means of the highest order stage at which the outputs of the first and second gate means are not the same logic level is at the second logic level and the output of the second gate means is at the first logic level, the third gate logic means including; fourth logic means connected to the outputs of the second gate means of each stage for producing a first logic level indicative of one decision other than an ''''equal'''' decision at any stage and a second logic level indicative of a decision other than said one decision; fifth logic means interconnecting an output at each stage and an input of the second gate means of each lower order stage for disabling the lower order stage when a decision other than than an ''''equal'''' decision or said one die decision is reached at the stage; sixth logic means connected to the outputs of the second gate means at each stage for producing a first logic level when an ''''equal'''' decision is reached at all stages and a second logic level when other than an ''''equal'''' decision is reached at any stage; and seventh logic means connected to the output of the fourth logic means and to an input of the sixth logic means for disabling the sixth logic means by producing said second logic level at its output when the output of the fourth logic means is at said first logic level.

Claim 36

In a digital comparator for comparing a multibit binary data number with a binary limit number having an equal number of bits, the combination of: a plurality of comparator stages each comprised of first gate means for producing the logic product of the true data bit value and the complement limit bit value at its output, and second gate means for producing the logic product of the complement data bit value and the true limit bit value at its output; third gate logic means for producing an ''''equal'''' logic condition when the outputs at each comparator stage are at the same logic level, a ''''greater than'''' logic condition when the output of the first gate means of the highest order stage at which the outputs of the first and second gate means are not the same logic level is at a first logic level and the output of the second gate means is at a second logic level, and a ''''less than'''' logic condition when the output of the first gate means of the highest order stage at which the outputs of the first and second gate means are not the same logic level is at the second logic level and the output of the second gate means is at the first logic level, the third gate logic means including; fourth logic means connected to the outputs of the second gate means of each stage for producing a first logic level indicative of one decision other than an ''''equal'''' decision at any stage and a second logic level indicative of a decision other than said one decision; fifth logic means interconnecting an output at each stage and an input of the second gate means of each lower order stage for disabling the lower order stage when a decision other than than an ''''equal'''' decision or said one die decision is reached at the stage; sixth logic means connected to the outputs of the second gate means at each stage for producing a first logic level when an ''''equal'''' decision is reached at all stages and a second logic level when other than an ''''equal'''' decision is reached at any stage; and seventh logic means connected to the output of the fourth logic means and to an input of the sixth logic means for disabling the sixth logic means by producing said second logic level at its output when the output of the fourth logic means is at said first logic level.

Claim 37

The combination defined in claim 18 wherein: the combination defined in claim 18 constitutes a decade in which the outputs of the decade; at least one additional decade as defined in claim 18 which is a lower order decade; eighth logic means connecting the outputs of the sixth logic means of each decade to the sixth logic means of the next lower order decade to enable the sixth logic means of the next lower order decade when the output of the sixth logic means of the higher order decade is at said first logic level indicative of an ''''equal'''' decision at all bits of the decade, and for disabling the sixth logic means of the next lower order decade if other than an ''''equal'''' decision is reached in the higher order decade; ninth logic means connected to the output of the fourth logic means of each decade for producing a logic level indicative of said one decision when said one decision is reached at a decade and an ''''equal'''' decision iS reached at all higher order decades; and tenth logic means connected to the output of the sixth logic means of the lowest order decade for producing a logic level indicative of an ''''equal'''' decision when an ''''equal'''' decision is reached at all decades.

Claim 38

The combination defined in claim 19 further characterized by: eleventh logic means connected to the outputs of the ninth and tenth logic means for producing a logic level indicative of said other decision when the ninth logic means does not indicate said one decision and tenth logic means does not indicate an ''''equal'''' decision.

Claim 39

The combination defined in claim 20 wherein one of the bits of the data and limit numbers represents the sign and further characterized by: logic means connected to the ninth and eleventh logic means for complementing the logic levels of the outputs of the ninth and tenth logic means when the signs of both the data number and limit number are negative and a decision other than ''''equal'''' is reached by the comparator.