Feedback current switch memory cell

Claim 1

A MEMORY SYSTEM COMPRISING A PLURALITY OF MEMORY CELLS, EACH MEMORY CELL COMPRISING AT LEAST FIRST, SECOND AND THIRD TRANSISTORS, THE COLLECTOR OF THE FIRST OF SAID TRANSISTORS BEING DIRECTLY CONNECTED TO THE BASE OF THE SECOND TRANSISTOR, A LOAD IMPEDANCE CONNECTED TO THE COLLECTOR OF SAID FIRST TRANSISTOR, AND A COMMON IMPEDANCE CONNECTED TO THE EMITTERS OF SAID FIRST, SECOND AND THIRD TRANSISTORS, EACH MEMORY CELL HAVING TWO QUIESCENT STATES, A FIRST STATE IN WHICH SAID FIRST TRANSISTOR IS CONDUCTIVE AND THE SECOND TRANSISTOR IS NONCONDUCTIVE, AND A SECOND STATE IN WHICH THE SECOND TRANSISTORS IS CONDUCTIVE AND THE FIRST TRANSISTOR IS NONCONDUCTIVE, SAID FIRST STATE DEFINING THE STORAGE OF A "1" BY SAID CELL, AND THE SECOND STATE DEFINING THE STORAGE OF A "0," AT LEAST THREE LINES CONNECTED TO EACH OF THE MEMORY CELLS, ONE OF SAID LINES BEING CONNECTED TO THE BASE OF SAID THIRD TRANSISTOR, MEANS, CONNECTED TO EACH OF SAID THREE LINES, FOR SELECTIVELY APPLYING PULSES TO THE BASES RESPECTIVELY OF EACH OF SAID FIRST, SECOND AND THRID TRANSISTORS IN EACH OF SAID MEMORY CELLS.