Frequency synthesizer using fractional division by digital techniques within a phase-locked loop

Claim 1

A FRACTIONAL DIVIDER PERFORMING, IN RESPONSE TO A FIRST SERIES OF PULSES APPLIED TO ITS INPUT, A SEQUENCE OF DIVISIONS OF THE FREQUENCY OF SAID FIRST SERIES OF PULSES BY A SERIES OF WHOLE NUMBER FACTORS TO PRODUCE A SECOND SERIES OF PULSES AT ITS OUTPUT IN RESPONSE THERETO, SAID SERIES OF WHOLE NUMBER FACTORS BEING SELECTED TO PRODUCE AN AVERAGE FREQUENCY OF SAID SECOND SERIES OF PULSES LESS THAN SAID FREQUENCY OF SAID FIRST SERIES OF PULSES BY SAID FACTOR WHEN AVERAGED OVER SAID SEQUENCE OF DIVISIONS, SAID DIVIDER COMPRISING: COUNTER MEANS FOR PRODUCING A DIVIDER OUTPUT PULSE IN RESPONSE TO A NUMBER OF SAID PULSES IN SAID FIRST SERIES APPLIED TO ITS INPUT EQUAL TO THE SMALLEST OF SAID WHOLE NUMBER FACTORS IN SAID SERIES OF WHOLE NUMBER FACTORS AND LOGIC MEANS COUPLED BETWEEN THE OUTPUT OF SAID DIVIDER AND THE INPUT OF SAID COUNTER MEANS AND RESPONSIVE TO SAID DIVIDER OUTPUT PULSES FOR WITHHOLDING, FOR EACH OF SAID DIVISIONS BY SAID SERIES OF WHOLE NUMBER FACTORS GREATER THAN SAID SMALLEST WHOLE NUMBER FACTOR, A NUMBER OF SAID PULSES WITHIN SAID FIRST SERIES OF PULSES FROM SAID COUNTER INPUT EQUAL TO THE DIFFENENCE BETWEEN THE WHOLE NUMBER FACTOR OF SAID DIVISION AND SAID SMALLEST WHOLE NUMBER FACTOR; SAID COUNTER MEANS COMPRISING: SELECTOR MEANS FOR SELECTING SAID SMALLEST WHOLE NUMBER FACTOR FROM A PLURALITY OF WHOLE NUMBERS.