Justification of operands in an arithmetic unit

Claim 1

A DATA PROCESSING APPARATUS INCLUDING THE COMBINATION COMPRISING AN ADDRESSABLE MAIN MEMORY FOR STORING A PLURALITY OF CHARACTERS OF INFORMATION INCLUDING BOTH DIVISOR AND DIVIDEND OPERANDS, A CONTROL PORTION OPERATIVELY CONNECTED TO SAID ADDRESSABLE MAIN MEMORY, SAID CONTROL PORTION INCLUDING A FIRST REGISTER INITIALLY STORING THE MAIN MEMORY ADDRESS OF THE LOW ORDER DIGIT OF THE DIVISOR, A SECOND REGISTER FOR STORING THE MAIN MEMORY ADDRESS OF THE HIGH ORDER DIGIT OF THE DIVIDEND, SCANNING MEANS CONNECTED TO THE OUTPUT OF SAID ADDRESSABLE MAIN MEMORY TO ALTERNATELY SCAN THE CONTENTS OF MAIN MEMORY LOCATIONS REFERENCED BY SAID FIRST AND SECOND REGISTERS AND TO SENSE FOR THE PRESENCE OF PUNCTUATION DEFINING A PARTICULAR DIGIT AS THE HIGH ORDER DIGIT OF THE DIVISOR, AND MEANS CONNECTED TO SAID SCANNING MEANS AND ADAPTED IN THE ABSENCE OF SAID DEFINING PUNCTUATION TO INCREMENT ONE OF SAID FIRST AND SECOND REGISTERS WHILE DECREMENTING SAID OTHER ONE OF SAID FIRST AND SECOND REGISTERS, SAID LAST-NAMED MEANS BEING FURTHER OPERATIVE UPON DETECTION OF SAID DEFINING PUNCTUATION TO THEREAFTER INITIATE THE ACTUAL DIVISION OPERATION BY THE METHOD OF OVER-AND-OVER SUBTRACTION.