Patent US3321639A successfully refreshed from Google Patents.
US3321639A
Expired / Lapsed
US
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Direct coupled, current mode logic
Assignee: General Electric Co
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Filing: 1962-12-03
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Granted: 1967-05-23
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Expires: 1982-12-03
Abstract
No abstract record available.
Inventors
- 👤 Robert Z Fowler
- 👤 Edgar W Seymour
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 01:43
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
113 words
A LOGIC CIRCUIT FOR PROCESSING DIGITAL SIGNALS COMPRISING: (A) A FIRST PAIR OF TRANSISTORS EACH HAVING BASE AND EMITTER ELECTRODES AND HAVING THEIR EMITTERS DIRECTLY COUPLED, TO FORM A DIFFERENTIAL AMPLIFIER AND RECEIVING DIGITAL INPUT SIGNALS AT THE BASE OF AT LEAST ONE OF SAID TRANSISTORS; (B) CLOCK MEANS FOR APPLYING SYNCHRONOUS PULSES TO THE EMITTERS OF SAID TRANSISTORS FOR GATING; AND (C) A SECOND PAIR OF TRANSISTORS, INTERCONNECTED AS A BISTABLE FLIP-FLOP AND HAVING ONE INPUT TERMINAL COUPLED TO ONE OF SAID TRANSISTORS AND ANOTHER INPUT TERMINAL TO THE OTHER OF SAID FIRST PAIR OF TRANSISTORS FOR CONTROL OF THE BISTABLE STATE THEREOF IN ACCORDANCE WITH THE OUTPUT OF SAID DIFFERENTIAL AMPLIFIER.
Claim 2
Dependent Claim
113 words
A LOGIC CIRCUIT FOR PROCESSING DIGITAL SIGNALS COMPRISING: (A) A FIRST PAIR OF TRANSISTORS EACH HAVING BASE AND EMITTER ELECTRODES AND HAVING THEIR EMITTERS DIRECTLY COUPLED, TO FORM A DIFFERENTIAL AMPLIFIER AND RECEIVING DIGITAL INPUT SIGNALS AT THE BASE OF AT LEAST ONE OF SAID TRANSISTORS; (B) CLOCK MEANS FOR APPLYING SYNCHRONOUS PULSES TO THE EMITTERS OF SAID TRANSISTORS FOR GATING; AND (C) A SECOND PAIR OF TRANSISTORS, INTERCONNECTED AS A BISTABLE FLIP-FLOP AND HAVING ONE INPUT TERMINAL COUPLED TO ONE OF SAID TRANSISTORS AND ANOTHER INPUT TERMINAL TO THE OTHER OF SAID FIRST PAIR OF TRANSISTORS FOR CONTROL OF THE BISTABLE STATE THEREOF IN ACCORDANCE WITH THE OUTPUT OF SAID DIFFERENTIAL AMPLIFIER.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1970-05-22 | 1970-11-21 | 1971-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1974-05-22 | 1974-11-21 | 1975-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1978-05-22 | 1978-11-21 | 1979-05-23 | $7700.00 | Window Closed / Lapsed |