Skew elimination system utilizing a plurality of buffer shift registers

Claim 1

IN A SYSTEM FOR READING A MAGNETIC TAPE HAVING BINARY CODED INFORMATION IN "1" AND "0" BIT FORM RECORDED THERON IN A PLURALITY OF PARALLEL TRACKS AND FOR ELIMINATING SKEW BETWEEN CORRESPONDING BITS ON SAID TRACKS: A PLURALITY OF PARALLEL READING AND BUFFER SHIFT REISTER CHANNELS CORRESPONDING TO SAID PLURALITY OF TRACKS, EACH OF SAID CHANNELS COMPRISING PICKUP MEANS HAVING FIRST AND SECOND OUTPUT CIRCUITS FOR RESPECTIVELY PROVIDING FIRST AND SECOND SIGNALS HAVING PULSES RESPONSIVE TO SAID "1" AND "0" BITS OF THE RESPECTIVE TRACK, AND A PLURALITY OF SERIALLY CONNECTED BUFFER REGISTER STAGES, EACH OF SAID STAGES COMPRISING THREE-STATE FLIP-FLOP CIRCUIT MEANS HAVING THREE INPUT CIRCUITS AND THREE OUTPUT CIRCUITS WITH MEANS THEREBETWEEN FOR AT ALL TIMES RESPECTIVELY PROVIDING SIGNALS HAVING ONE PREDETERMINED POTENTIAL STATE IN TWO OF THE OUTPUT CIRCUITS AND ANOTHER PREDETERMINED POTENTIAL STATE IN THE REMAINING OUTPUT CIRCUIT, SAID LASTNAMES MEANS CHANGING THE POTENTIAL STATE OF ONE OUTPUT CIRCUIT FROM SAID ONE STATE TO SAID OTHER STATE RESPONSIVE TO APPLICATION OF A PULSE TO THE CORRESPONDING INPUT CIRCUIT WHEREBY THE POTENTIAL OF ONE OF THE REMAINING TWO OUTPUT CIRCUITS IS CHANGED FROM SAID OTHER STATE TO SAID ONE STATE, AND GATING MEANS RESPECTIVELY COUPLED TO TWO OF THE INPUT CIRCUITS OF EACH OF SAID FLIP-FLOP CIRCUIT MEANS, THE GATING MEANS OF THE FIRST OF SAID STAGES BEING RESPECTIVELY COUPLED TO SAID FIRST AND SECOND OUTPUT CIRCUITS OF SAID PICKUP MEANS, THE TWO OUTPUT CIRCUITS OF EACH SAID FLIP-FLOP CIRCUIT MEANS CORRESPONDING TO SAID TWO INPUT CIRCUITS THEREOF BEING COUPLED RESPECTIVELY TO THE GATING MEANS OF THE NEXT SUCCESSIVE STAGE, THE THIRD OUTPUT CIRCUIT OF EACH OF SAID FLIP-FLOP CIRCUIT MEANS BEING COUPLED TO THE GATING MEANS OF THE SAME STAGE FOR GATING A SIGNAL TO THE RESPECTIVE INPUT CIRCUITS IN RESPONSIVE TO SAID THIRD OUTPUT CIRCUIT HAVING SAID OTHER POTENTIAL STATE THEREON, THE THIRD OUTPUT CIRCUIT OF THE FLIP-FLOP CIRCUIT MEANS OF EACH OF SAID STAGES ABOVE THE FIRST BEING COUPLED TO THE THIRD INPUT CIRCUIT OF THE FLIP-FLOP CIRCUIT MEANS OF THE NEXT PRECEDING STAGE FOR APPLYING A PULSE THERETO IN RESPONSE TO SAID THIRD OUTPUT CIRCUIT BEING IN SAID ONE POTENTIAL STATE; FINAL MEANS COUPLED TO THE THIRD OUTPUT CIRCUIT OF THE FLIP-FLOP CIRCUIT MEANS OF THE LAST STAGE OF ALL OF SAID CHANNELS FOR PROVIDING AN INDICATING SIGNAL RESPONSIVE TO ALL OF SAID LAST-NAMED THIRD OUTPUT CIRCUITS BEING IN SAID ONE STATE; AND FINAL GATING MEANS RESPECTIVELY COUPLING SAID TWO OUTPUT CIRCUITS OF SAID FLIP-FLOP CIRCUIT MEANS OF THE LAST STAGE OF ALL OF SAID CHANNELS TO OUTPUT CIRCUIT MEANS CORRESPONDING TO SAID TRACKS, SAID FINAL MEANS BEING COUPLED TO SAID FINAL GATING MEANS FOR SIMULTANEOUSLY GATING SIGNALS TO SAID OUTPUT CIRCUIT MEANS FROM SAID TWO OUTPUT CIRCUITS OF ALL OF SAID LAST STAGES RESPONSIVE TO SAID INDICATING SIGNAL.