Skew correction system

Claim 1

A SYSTEM FOR CORRECTING SKEW OF A MOVING STORAGE MEDIUM CONTAINING A PAIR OF SPACED TRACKS AND AN INTERMEDIATE TRACK FOR THE STORAGE OF BITS OF INFORMATION, A CHARACTER OF INFORMATION BEING REPRESENTED BY THE PRESENCE OR ABSENCE OF BITS ALONG A LINE TRANSVERSE TO THE DIRECTION OF THE TRACKS, SAID SYSTEM COMPRISING A SYNCHRONIZING CHARACTER CONSISTING OF BITS IN SAID TRACKS AND POSITIONED IN A LINE TRANSVERSE THERETO, A TRANSDUCER FOR EACH OF THE TRACKS, THE PLURALITY OF TRANSDUCERS BEING ADAPTED TO READ THE BITS SIMULTANEOUSLY IN THE ABSENCE OF SKEW, AND IN THE PRESENCE OF SKEW BIT IN ONE OF SAID PAIR OF TRACKS BEING READ PRIOR TO THE BIT IN THE OTHER OF SAID PAIR OF TRACKS, A LOGICAL CIRCUIT FOR EACH OF SAID PAIR OF TRACKS OF SAID MEDIUM COUPLED TO THE TRANSDUCER FOR EACH RESPECTIVE TRACK, THE RESPECTIVE LOGICAL CIRCUITS INCLUDING DELAY MEANS FOR DELAYING THE OUTPUTS FROM THE RESPECTIVE TRANSDUCERS DIFFERENT AMOUNTS SO THAT THE OUTPUTS CORRESPONDING TO THE BITS OF THE SYNCHRONIZING CHARACTER WILL APPEAR SIMULTANEOUSLY AT THE OUTPUTS OF SAID RESPECTIVE LOGICAL CIRCUITS, THE DELAY MEANS IN EACH LOGICAL CIRCUIT BEING COUPLED TO RECEIVE THE OUTPUT FROM THE TRANSDUCER WITH WHICH IT IS ASSOCIATED, SAID LOGICAL CIRCUITS EACH FURTHER INCLUDING SEPARATE COINCIDENCE CIRCUITS EACH HAVING AN INPUT COUPLED TO A DIFFERENT POINT ALONG THE DELAY MEANS IN THE RESPECTIVE LOGICAL CIRCUIT, MEANS IN EACH LOGICAL CIRCUIT COUPLED TO A SECOND INPUT OF EACH OF SAID COINCIDENCE CIRCUITS FOR SUPPLYING AN ENABLING PULSE TO EACH SUCH COINCIDENCE CIRCUIT AT DIFFERENT TIMES, AND MEANS FOR COUPLING SAID TRANSDUCER OF SAID INTERMEDIATE TRACK WITH EACH OF SAID LOGICAL CIRCUITS.

Claim 2

A SYSTEM FOR CORRECTING SKEW OF A MOVING STORAGE MEDIUM CONTAINING A PAIR OF SPACED TRACKS AND AN INTERMEDIATE TRACK FOR THE STORAGE OF BITS OF INFORMATION, A CHARACTER OF INFORMATION BEING REPRESENTED BY THE PRESENCE OR ABSENCE OF BITS ALONG A LINE TRANSVERSE TO THE DIRECTION OF THE TRACKS, SAID SYSTEM COMPRISING A SYNCHRONIZING CHARACTER CONSISTING OF BITS IN SAID TRACKS AND POSITIONED IN A LINE TRANSVERSE THERETO, A TRANSDUCER FOR EACH OF THE TRACKS, THE PLURALITY OF TRANSDUCERS BEING ADAPTED TO READ THE BITS SIMULTANEOUSLY IN THE ABSENCE OF SKEW, AND IN THE PRESENCE OF SKEW BIT IN ONE OF SAID PAIR OF TRACKS BEING READ PRIOR TO THE BIT IN THE OTHER OF SAID PAIR OF TRACKS, A LOGICAL CIRCUIT FOR EACH OF SAID PAIR OF TRACKS OF SAID MEDIUM COUPLED TO THE TRANSDUCER FOR EACH RESPECTIVE TRACK, THE RESPECTIVE LOGICAL CIRCUITS INCLUDING DELAY MEANS FOR DELAYING THE OUTPUTS FROM THE RESPECTIVE TRANSDUCERS DIFFERENT AMOUNTS SO THAT THE OUTPUTS CORRESPONDING TO THE BITS OF THE SYNCHRONIZING CHARACTER WILL APPEAR SIMULTANEOUSLY AT THE OUTPUTS OF SAID RESPECTIVE LOGICAL CIRCUITS, THE DELAY MEANS IN EACH LOGICAL CIRCUIT BEING COUPLED TO RECEIVE THE OUTPUT FROM THE TRANSDUCER WITH WHICH IT IS ASSOCIATED, SAID LOGICAL CIRCUITS EACH FURTHER INCLUDING SEPARATE COINCIDENCE CIRCUITS EACH HAVING AN INPUT COUPLED TO A DIFFERENT POINT ALONG THE DELAY MEANS IN THE RESPECTIVE LOGICAL CIRCUIT, MEANS IN EACH LOGICAL CIRCUIT COUPLED TO A SECOND INPUT OF EACH OF SAID COINCIDENCE CIRCUITS FOR SUPPLYING AN ENABLING PULSE TO EACH SUCH COINCIDENCE CIRCUIT AT DIFFERENT TIMES, AND MEANS FOR COUPLING SAID TRANSDUCER OF SAID INTERMEDIATE TRACK WITH EACH OF SAID LOGICAL CIRCUITS.