Patent US3264567A successfully refreshed from Google Patents.
US3264567A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Binary coded decimal counter circuits
Assignee: RCA Corp
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Filing: 1964-07-02
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Granted: 1966-08-02
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Expires: 1984-07-02
Abstract
No abstract record available.
Inventors
- 👤 Prieto Anthony
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 00:55
CPC Classifications
H; H03; H03K; H03K21/00
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
171 words
A STAGE OF A BINARY CODED DECIMAL COUNTER COMPRISING, IN COMBINATION: FOUR TWO-STATE DEVICES FOR STORING THE 20, 21, 22 AND 23 BITS, RESPECTIVELY, OF A BINARY CODED DECIMAL NUMBER; FIRST, SECOND AND THIRD LOGIC CIRCUITS, CONNECTED TO THE 21, 22 AND 23 TWO-STATE DEVICES, RESPECTIVELY, FOR APPLYING TRIGGERING SIGNALS TO SAID DEVICES, AND SAID THIRD LOGIC CIRCUITS FOR ALSO PRODUCING A CARRY SIGNAL; MEANS FOR APPLYING THE PULSES TO BE COUNTED TO THE 20 TWO-STATE DEVICE, AND THE FIRST AND SECOND LOGIC CIRCUITS; MEANS FOR APPLYING AN OUTPUT OF THE 20 TWO-STATE DEVICE TO ALL THREE LOGIC CIRCUITS; MEANS FOR APPLYING AN OUTPUT OF THE 21 TWO-STATE DEVICE TO THE SECOND LOGIC CIRCUITS; MEANS FOR APPLYING AN OUTPUT OF THE 22 TWO-STATE DEVICE TO THE THIRD LOGIC CIRCUIT; MEANS FOR APPLYING ONE OUTPUT OF THE 23 TWO-STATE DEVICE TO THE THIRD LOGIC CIRCUIT AND THE COMPLEMENT OF SAID OUTPUT TO THE FIRST LOGIC CIRCUIT; AND MEANS FOR APPLYING AN OUTPUT FROM THE SECOND LOGIC CIRCUIT TO THE THIRD LOGIC CIRCUIT.
Claim 2
Dependent Claim
171 words
A STAGE OF A BINARY CODED DECIMAL COUNTER COMPRISING, IN COMBINATION: FOUR TWO-STATE DEVICES FOR STORING THE 20, 21, 22 AND 23 BITS, RESPECTIVELY, OF A BINARY CODED DECIMAL NUMBER; FIRST, SECOND AND THIRD LOGIC CIRCUITS, CONNECTED TO THE 21, 22 AND 23 TWO-STATE DEVICES, RESPECTIVELY, FOR APPLYING TRIGGERING SIGNALS TO SAID DEVICES, AND SAID THIRD LOGIC CIRCUITS FOR ALSO PRODUCING A CARRY SIGNAL; MEANS FOR APPLYING THE PULSES TO BE COUNTED TO THE 20 TWO-STATE DEVICE, AND THE FIRST AND SECOND LOGIC CIRCUITS; MEANS FOR APPLYING AN OUTPUT OF THE 20 TWO-STATE DEVICE TO ALL THREE LOGIC CIRCUITS; MEANS FOR APPLYING AN OUTPUT OF THE 21 TWO-STATE DEVICE TO THE SECOND LOGIC CIRCUITS; MEANS FOR APPLYING AN OUTPUT OF THE 22 TWO-STATE DEVICE TO THE THIRD LOGIC CIRCUIT; MEANS FOR APPLYING ONE OUTPUT OF THE 23 TWO-STATE DEVICE TO THE THIRD LOGIC CIRCUIT AND THE COMPLEMENT OF SAID OUTPUT TO THE FIRST LOGIC CIRCUIT; AND MEANS FOR APPLYING AN OUTPUT FROM THE SECOND LOGIC CIRCUIT TO THE THIRD LOGIC CIRCUIT.
References Cited (Backward Citations)
US2889468A
Cited
US3183369A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1969-08-01 | 1970-01-31 | 1970-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1973-08-01 | 1974-01-31 | 1974-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1977-08-01 | 1978-01-31 | 1978-08-02 | $7700.00 | Window Closed / Lapsed |