Parity bit indicator

Claim 1

APPARATUS FOR PRODUCING A PARITY BIT INDICATIVE OF AN ADDRESS SELECTED IN A MEMORY, COMPRISING A PLURALITY OF BISTABLE CORES NORMALLY RESIDING IN THE SAME STATE, ADDRESS SELECTION MEANS COUPLED TO EACH OF SAID CORES SO THAT FOR ANY ADDRESS, TWO CORES WILL GENERATE AN OUTPUT INDICATIVE OF ODD OR EVEN PARITY, A PAIR OF OUTPUT CIRCUITS COUPLED TO SAID TWO CORES, AND CHECKING MEANS COUPLED TO SAID OUTPUT CIRCUITS COMPORISING A PLURALITY OF GATING CIRCUITS, MEANS INCLUDING A FIRST PAIR OF SAID GATING CIRCUITS FOR INDICATING WHEN SAID PAIR OF OUTPUTS HAS THE SAME OUTPUT SIGNAL THEREON, AND MEANS INCLUDING A SECOND PAIR OF GATING CIRCUITS FOR INDICATING WHEN AN INPUT PARITY BIT DOES NOT MATCH AN OUTPUT PARITY BIT.