Digital character magnitude comparator

Claim 1

APPARATUS FOR SERIALLY CONTROLLABLY COMPARING LEAST- OR MOST-SIGNIFICANT-CHARACTER-FIRST THE CHARACTERS OF FIRST AND SECOND UNITS OF DATA WHEREIN EACH CHARACTER IS A CODED COMBINATION OF N BITS IN PARALLEL, THE BITS BEING REPRESENTED BY PUSH-PULL SIGNALS, COMPRISING: AT LEAST N-1 BIT COMPARATORS, EACH OF SAID BIT COMPARATORS INCLUDING A FIRST "AND" CIRCUIT RESPONSIVE TO THE FIRST PHASE OF THE PUSHPULL SIGNAL REPRESENTING A BIT OF THE FIRST UNIT OF DATA AND TO THE OPPOSITE PHASE OF THE PUSH-PULL SIGNAL REPRESENTING THE CORRESPONDING BIT OF THE SECOND UNIT OF INFORMATION, A SECOND "AND" GATE RESPONSIVE TO THE OPPOSITE PHASE OF THE PUSH-PULL SIGNAL REPRESENTING SAID BIT OF THE FIRST UNIT OF INFORMATION AND THE FIRST PHASE OF THE PUSH-PULL SIGNAL REPRESENTING SAID CORRESPONDING BIT OF SAID SECOND UNIT OF INFORMATION, A THIRD "AND" GATE RESPONSIVE TO THE FIRST PHASE SIGNAL OF PUSH-PULL SIGNALS REPRESENTING SAID BITS OF THE FIRST "AND" SECOND UNITS OF INFORMATION, A FOURTH AND GATE REPONSIVE TO THE OPPOSITE PHASE OF THE PUSH-PULL SIGNALS REPRESENTING SAID BITS OF SAID FIRST AND SECOND UNITS OF INFORMATION, A FIRST "OR" CIRCUIT RESPONSIVE TO SAID THIRD AND FOURTH "AND" GATES, ALL OF THE "AND" GATES OF THE LOWER ORDER BIT COMPARATORS UNDER CONTROL OF THE FIRST "OR" CIRCUIT OF THE NEXT HIGHER BIT COMPARATOR; A SECOND "OR" CIRCUIT RESPONSIVE TO THE FIRST "AND" CIRCUITS OF ALL OF SAID BIT COMPARATORS; A FIRST FLIP-FLOP HAVING A SET AND A RESET INPUT TERMINAL, SAID SET INPUT TERMINAL BEING RESPONSIOVE TO SAID SECOND "OR" CIRCUIT, A THIRD "OR" CIRCUIT RESPONSIVE TO THE SECOND "AND" GATES OF ALL OF SAID BIT COMPARATORS; A SECOND FLIP-FLOP HAVING A SET AND A RESET INPUT TERMINAL, SAID SET INPUT TERMINAL BEING RESPONSIVE TO SAID THIRD "OR" CIRCUIT; THE RESET INPUT TERMINAL OF THE FIRST FLIP-FLOP BEING RESPONSIVE TO SAID THIRD "OR" CIRCUIT; THE RESET INPUT TERMINAL OF SAID SECOND FLIP-FLOP BEING RESPONSIVE TO SAID SECOND "OR" CIRCUIT; MEANS CONTROLLABLY RESPONSIVE TO SAID FIRST AND SECOND FLIP-FLOP FOR CONTROLLING THE OPERATION OF THE "AND" GATES OF THE HIGHEST ORDER BIT COMPARATOR.